Changeset 46bbccb in mainline


Ignore:
Timestamp:
2006-03-15T00:52:44Z (19 years ago)
Author:
Martin Decky <martin@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
5e7b926
Parents:
96e08225
Message:

simplify register names

Location:
arch/ppc32/loader
Files:
1 deleted
2 edited

Legend:

Unmodified
Added
Removed
  • arch/ppc32/loader/asm.S

    r96e08225 r46bbccb  
    2828
    2929#include "regname.h"
    30 #include "spr.h"
    3130
    3231.data
     
    165164       
    166165        li r3, 0
    167         ori     r3, r3, (HID0_ICE | HID0_DCE | HID0_ICFI | HID0_DCI)
    168         mfspr r4, SPRN_HID0
     166        ori     r3, r3, (hid0_ice | hid0_dce | hid0_icfi | hid0_dci)
     167        mfspr r4, hid0
    169168        or r5, r4, r3
    170169        isync
    171         mtspr SPRN_HID0, r5
     170        mtspr hid0, r5
    172171        sync
    173172        isync
     
    175174        # Enable instruction cache
    176175       
    177         ori     r5, r4, HID0_ICE
    178         mtspr SPRN_HID0, r5
     176        ori     r5, r4, hid0_ice
     177        mtspr hid0, r5
    179178        sync
    180179        isync
     
    185184        mtlr r3
    186185        blr
    187 
  • arch/ppc32/loader/regname.h

    r96e08225 r46bbccb  
    2727 */
    2828
    29 #ifndef __REGNAME_H__
    30 #define __REGNAME_H__
     29#ifndef __ppc32_REGNAME_H__
     30#define __ppc32_REGNAME_H__
    3131
    3232/* Condition Register Bit Fields */
     
    189189#define sprg3   275
    190190#define prv             287
     191#define hid0    1008
     192
     193/* MSR bits */
     194#define msr_ir  (1 << 4)
     195#define msr_dr  (1 << 5)
     196
     197/* HID0 bits */
     198#define hid0_ice        (1 << 15)
     199#define hid0_dce        (1 << 14)
     200#define hid0_icfi       (1 << 11)
     201#define hid0_dci        (1 << 10)
     202
     203/* Cache sizes */
     204#define L1_CACHE_LINES (128 * 8)
     205#define L1_CACHE_BYTES 5
    191206
    192207#endif
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