Changeset 46bbccb in mainline

Timestamp:

2006-03-15T00:52:44Z (19 years ago)

Author:

Martin Decky <martin@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

5e7b926

Parents:

96e08225

Message:

simplify register names

Location:

arch/ppc32/loader

Files:

• asm.S (modified) (4 diffs)
• regname.h (modified) (2 diffs)
• spr.h (deleted)

arch/ppc32/loader/asm.S

@@ -28 +28 @@
 
 #include "regname.h"
-#include "spr.h"
 
 .data
@@ -165 +164 @@
         
         li r3, 0
-        ori     r3, r3, (HID0_ICE | HID0_DCE | HID0_ICFI | HID0_DCI)
-        mfspr r4, SPRN_HID0
+        ori     r3, r3, (hid0_ice | hid0_dce | hid0_icfi | hid0_dci)
+        mfspr r4, hid0
         or r5, r4, r3
         isync
-        mtspr SPRN_HID0, r5
+        mtspr hid0, r5
         sync
         isync
@@ -175 +174 @@
         # Enable instruction cache
         
-        ori     r5, r4, HID0_ICE
-        mtspr SPRN_HID0, r5
+        ori     r5, r4, hid0_ice
+        mtspr hid0, r5
         sync
         isync
@@ -185 +184 @@
         mtlr r3
         blr
-

arch/ppc32/loader/regname.h

@@ -27 +27 @@
  */
 
-#ifndef __REGNAME_H__
-#define __REGNAME_H__
+#ifndef __ppc32_REGNAME_H__
+#define __ppc32_REGNAME_H__
 
 /* Condition Register Bit Fields */
@@ -189 +189 @@
 #define sprg3   275
 #define prv             287
+#define hid0    1008
+
+/* MSR bits */
+#define msr_ir  (1 << 4)
+#define msr_dr  (1 << 5)
+
+/* HID0 bits */
+#define hid0_ice        (1 << 15)
+#define hid0_dce        (1 << 14)
+#define hid0_icfi       (1 << 11)
+#define hid0_dci        (1 << 10)
+
+/* Cache sizes */
+#define L1_CACHE_LINES (128 * 8)
+#define L1_CACHE_BYTES 5
 
 #endif