Changeset 5f310ec8 in mainline

Timestamp:

2015-09-16T18:52:13Z (9 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

a1d636e

Parents:

996dc042

Message:

Access CP15 register 8 wrt. target architecture and implementation

CP15 register 8 controls the TLB(s).

• Do not define macros for functionality which is not supported by the target architecture or implementation.
• For ARM920T implementation, do not use TLBIMVA in invalidate_page().

Location:

kernel/arch/arm32

Files:

• include/arch/cp15.h (modified) (1 diff)
• src/mm/tlb.c (modified) (1 diff)

kernel/arch/arm32/include/arch/cp15.h

@@ -415 +415 @@
 
 /* TLB maintenance */
+#if defined(PROCESSOR_ARCH_armv7_a)
 CONTROL_REG_GEN_WRITE(TLBIALLIS, c8, 0, c3, 0); /* Inner shareable */
 CONTROL_REG_GEN_WRITE(TLBIMVAIS, c8, 0, c3, 1); /* Inner shareable */
 CONTROL_REG_GEN_WRITE(TLBIASIDIS, c8, 0, c3, 2); /* Inner shareable */
 CONTROL_REG_GEN_WRITE(TLBIMVAAIS, c8, 0, c3, 3); /* Inner shareable */
+#endif
 
 CONTROL_REG_GEN_WRITE(ITLBIALL, c8, 0, c5, 0);
 CONTROL_REG_GEN_WRITE(ITLBIMVA, c8, 0, c5, 1);
+#if defined(PROCESSOR_ARCH_armv6) || defined(PROCESSOR_ARCH_armv7_a)
 CONTROL_REG_GEN_WRITE(ITLBIASID, c8, 0, c5, 2);
+#endif
 
 CONTROL_REG_GEN_WRITE(DTLBIALL, c8, 0, c6, 0);
 CONTROL_REG_GEN_WRITE(DTLBIMVA, c8, 0, c6, 1);
+#if defined(PROCESSOR_ARCH_armv6) || defined(PROCESSOR_ARCH_armv7_a)
 CONTROL_REG_GEN_WRITE(DTLBIASID, c8, 0, c6, 2);
+#endif
 
 CONTROL_REG_GEN_WRITE(TLBIALL, c8, 0, c7, 0);
+#if !defined(PROCESSOR_arm920t)
 CONTROL_REG_GEN_WRITE(TLBIMVA, c8, 0, c7, 1);
+#endif
+#if defined(PROCESSOR_ARCH_armv6) || defined(PROCESSOR_ARCH_armv7_a)
 CONTROL_REG_GEN_WRITE(TLBIASID, c8, 0, c7, 2);
+#endif
+#if defined(PROCESSOR_ARCH_armv7_a)
 CONTROL_REG_GEN_WRITE(TLBIMVAA, c8, 0, c7, 3);
-
+#endif
+
+#if defined(PROCESSOR_ARCH_armv7_a)
 CONTROL_REG_GEN_WRITE(TLBIALLHIS, c8, 4, c3, 0); /* Inner shareable */
 CONTROL_REG_GEN_WRITE(TLBIMVAHIS, c8, 4, c3, 1); /* Inner shareable */
 CONTROL_REG_GEN_WRITE(TLBIALLNSNHIS, c8, 4, c3, 4); /* Inner shareable */
-
+#endif
+
+#if defined(PROCESSOR_ARCH_armv7_a)
 CONTROL_REG_GEN_WRITE(TLBIALLH, c8, 4, c7, 0);
 CONTROL_REG_GEN_WRITE(TLBIMVAH, c8, 4, c7, 1);
 CONTROL_REG_GEN_WRITE(TLBIALLNSNHS, c8, 4, c7, 4);
+#endif
 
 /* c9 are performance monitoring resgisters */

kernel/arch/arm32/src/mm/tlb.c

@@ -79 +79 @@
 static inline void invalidate_page(uintptr_t page)
 {
+#if defined(PROCESSOR_arm920t)
+        ITLBIMVA_write(page);
+        DTLBIMVA_write(page);
+#else
         //TODO: What about TLBIMVAA?
         TLBIMVA_write(page);
+#endif
         /*
          * "A TLB maintenance operation is only guaranteed to be complete after