Changeset a1d636e in mainline

Timestamp:

2015-09-17T07:19:30Z (9 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

f834cc32

Parents:

5f310ec8

Message:

Access CP15 register 2 wrt. target architecture and implementation

CP15 register 2 controls the Translation Table Base and Translation
Table Base Control registers.

• Do not define macros for functionality which is not supported by the target architecture or implementation.
• ARMv4 and ARMv5 define bits 13:0 as unpredictable/should be zero.

Files:

• boot/arch/arm32/src/mm.c (modified) (1 diff)
• kernel/arch/arm32/include/arch/cp15.h (modified) (3 diffs)
• kernel/arch/arm32/include/arch/mm/page.h (modified) (1 diff)

boot/arch/arm32/src/mm.c

@@ -189 +189 @@
          */
         uint32_t val = (uint32_t)boot_pt & TTBR_ADDR_MASK;
+#if defined(PROCESSOR_ARCH_armv6) || defined(PROCESSOR_ARCH_armv7_a)
+        // FIXME: TTBR_RGN_WBWA_CACHE is unpredictable on ARMv6
         val |= TTBR_RGN_WBWA_CACHE | TTBR_C_FLAG;
+#endif
         TTBR0_write(val);
 }

kernel/arch/arm32/include/arch/cp15.h

@@ -309 +309 @@
 enum {
         TTBR_ADDR_MASK = 0xffffff80,
+#if defined(PROCESSOR_ARCH_armv6) || defined(PROCESSOR_ARCH_armv7_a)
         TTBR_NOS_FLAG = 1 << 5,
         TTBR_RGN_MASK = 0x3 << 3,
@@ -317 +318 @@
         TTBR_S_FLAG = 1 << 1,
         TTBR_C_FLAG = 1 << 0,
+#endif
 };
 CONTROL_REG_GEN_READ(TTBR0, c2, 0, c0, 0);
 CONTROL_REG_GEN_WRITE(TTBR0, c2, 0, c0, 0);
+
+#if defined(PROCESSOR_ARCH_armv6) || defined(PROCESSOR_ARCH_armv7_a)
 CONTROL_REG_GEN_READ(TTBR1, c2, 0, c0, 1);
 CONTROL_REG_GEN_WRITE(TTBR1, c2, 0, c0, 1);
 CONTROL_REG_GEN_READ(TTBCR, c2, 0, c0, 2);
 CONTROL_REG_GEN_WRITE(TTBCR, c2, 0, c0, 2);
-
+#endif
+
+#if defined(PROCESSOR_ARCH_armv7)
 CONTROL_REG_GEN_READ(HTCR, c2, 4, c0, 2);
 CONTROL_REG_GEN_WRITE(HTCR, c2, 4, c0, 2);
@@ -339 +345 @@
 CONTROL_REG_GEN_READ(VTTBRH, c2, 0, c2, 6);
 CONTROL_REG_GEN_WRITE(VTTBRH, c2, 0, c2, 6);
+#endif
 
 CONTROL_REG_GEN_READ(DACR, c3, 0, c0, 0);

kernel/arch/arm32/include/arch/mm/page.h

@@ -154 +154 @@
 {
         uint32_t val = (uint32_t)pt & TTBR_ADDR_MASK;
+#if defined(PROCESSOR_ARCH_armv6) || defined(PROCESSOR_ARCH_armv7_a)
+        // FIXME: TTBR_RGN_WBWA_CACHE is unpredictable on ARMv6
         val |= TTBR_RGN_WBWA_CACHE | TTBR_C_FLAG;
+#endif
         TTBR0_write(val);
 }