Ignore:
Timestamp:
2013-01-19T19:01:09Z (12 years ago)
Author:
Jan Vesely <jano.vesely@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
c3213bb
Parents:
26e3db2
Message:

arm32, page_fault: Use cp15 helpers.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • kernel/arch/arm32/src/mm/page_fault.c

    r26e3db2 r612edca  
    3434 */
    3535#include <panic.h>
     36#include <arch/cp15.h>
    3637#include <arch/exception.h>
    3738#include <arch/mm/page_fault.h>
     
    127128}
    128129
    129 
    130 /** Returns value stored in comnbined/data fault status register.
    131  *
    132  *  @return Value stored in CP15 fault status register (FSR).
    133  *
    134  *  "VMSAv6 added a fifth fault status bit (bit[10]) to both the IFSR and DFSR.
    135  *  It is IMPLEMENTATION DEFINED how this bit is encoded in earlier versions of
    136  *  the architecture. A write flag (bit[11] of the DFSR) has also been
    137  *  introduced."
    138  *  ARM Architecture Reference Manual version i ch. B4.6 (PDF p. 719)
    139  *
    140  *  See ch. B4.9.6 for location of data/instruction FSR.
    141  *
    142  */
    143 static inline fault_status_t read_data_fault_status_register(void)
    144 {
    145         fault_status_t fsu;
    146        
    147         /* Combined/Data fault status is stored in CP15 register 5, c0. */
    148         asm volatile (
    149                 "mrc p15, 0, %[dummy], c5, c0, 0"
    150                 : [dummy] "=r" (fsu.raw)
    151         );
    152        
    153         return fsu;
    154 }
    155 
    156 /** Returns DFAR (fault address register) content.
    157  *
    158  * This register is equivalent to FAR on pre armv6 machines.
    159  *
    160  * @return DFAR (fault address register) content (address that caused a page
    161  *         fault)
    162  */
    163 static inline uintptr_t read_data_fault_address_register(void)
    164 {
    165         uintptr_t ret;
    166        
    167         /* fault adress is stored in CP15 register 6 */
    168         asm volatile (
    169                 "mrc p15, 0, %[ret], c6, c0, 0"
    170                 : [ret] "=r" (ret)
    171         );
    172        
    173         return ret;
    174 }
    175 
    176130#if defined(PROCESSOR_ARCH_armv4) | defined(PROCESSOR_ARCH_armv5)
    177131/** Decides whether read or write into memory is requested.
     
    244198void data_abort(unsigned int exc_no, istate_t *istate)
    245199{
    246         const uintptr_t badvaddr = read_data_fault_address_register();
    247         const fault_status_t fsr = read_data_fault_status_register();
     200        const uintptr_t badvaddr = DFAR_read();
     201        const fault_status_t fsr = { .raw = DFSR_read() };
    248202        const dfsr_source_t source = fsr.raw & DFSR_SOURCE_MASK;
    249203
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