Changeset 63530c62 in mainline for kernel/genarch/src/kbd/z8530.c
- Timestamp:
- 2006-10-14T19:31:03Z (18 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- e3890b3f
- Parents:
- 7dcf22a
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
kernel/genarch/src/kbd/z8530.c
r7dcf22a r63530c62 61 61 bool z8530_belongs_to_kernel = true; 62 62 63 static z8530_t z8530; /**< z8530 device structure. */ 64 static irq_t z8530_irq; /**< z8530's IRQ. */ 65 63 66 static void z8530_suspend(chardev_t *); 64 67 static void z8530_resume(chardev_t *); … … 85 88 86 89 /** Initialize z8530. */ 87 void z8530_init( void)90 void z8530_init(devno_t devno, inr_t inr, uintptr_t vaddr) 88 91 { 89 92 chardev_initialize("z8530_kbd", &kbrd, &ops); 90 93 stdin = &kbrd; 91 94 95 z8530.devno = devno; 96 z8530.reg = (uint8_t *) vaddr; 97 98 irq_initialize(&z8530_irq); 99 z8530_irq.devno = devno; 100 z8530_irq.inr = inr; 101 z8530_irq.claim = z8530_claim; 102 z8530_irq.handler = z8530_irq_handler; 103 irq_register(&z8530_irq); 104 92 105 sysinfo_set_item_val("kbd", NULL, true); 93 sysinfo_set_item_val("kbd.irq", NULL, 0); 94 sysinfo_set_item_val("kbd.address.virtual", NULL, (uintptr_t) kbd_virt_address); 95 96 (void) z8530_read_a(RR8); 106 sysinfo_set_item_val("kbd.devno", NULL, devno); 107 sysinfo_set_item_val("kbd.inr", NULL, inr); 108 sysinfo_set_item_val("kbd.address.virtual", NULL, vaddr); 109 110 (void) z8530_read_a(&z8530, RR8); 97 111 98 112 /* … … 100 114 * to set FHC UART interrupt state to idle. 101 115 */ 102 z8530_write_a( WR0, WR0_TX_IP_RST);103 104 z8530_write_a( WR1, WR1_IARCSC); /* interrupt on all characters */116 z8530_write_a(&z8530, WR0, WR0_TX_IP_RST); 117 118 z8530_write_a(&z8530, WR1, WR1_IARCSC); /* interrupt on all characters */ 105 119 106 120 /* 8 bits per character and enable receiver */ 107 z8530_write_a( WR3, WR3_RX8BITSCH | WR3_RX_ENABLE);121 z8530_write_a(&z8530, WR3, WR3_RX8BITSCH | WR3_RX_ENABLE); 108 122 109 z8530_write_a( WR9, WR9_MIE); /* Master Interrupt Enable. */123 z8530_write_a(&z8530, WR9, WR9_MIE); /* Master Interrupt Enable. */ 110 124 } 111 125 … … 140 154 while(!(ch = active_read_buff_read())) { 141 155 uint8_t x; 142 while (!(z8530_read_a( RR0) & RR0_RCA))156 while (!(z8530_read_a(&z8530, RR0) & RR0_RCA)) 143 157 ; 144 x = z8530_read_a( RR8);158 x = z8530_read_a(&z8530, RR8); 145 159 if (x != IGNORE_CODE) { 146 160 if (x & KEY_RELEASE) … … 161 175 uint8_t x; 162 176 163 while (z8530_read_a( RR0) & RR0_RCA) {164 x = z8530_read_a( RR8);177 while (z8530_read_a(&z8530, RR0) & RR0_RCA) { 178 x = z8530_read_a(&z8530, RR8); 165 179 if (x != IGNORE_CODE) { 166 180 if (x & KEY_RELEASE) … … 174 188 irq_ownership_t z8530_claim(void) 175 189 { 176 return (z8530_read_a( RR0) & RR0_RCA);190 return (z8530_read_a(&z8530, RR0) & RR0_RCA); 177 191 } 178 192
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