Changeset 7f1c620 in mainline for arch/ia64/src/mm/tlb.c

Timestamp:

2006-07-04T17:17:56Z (19 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

0ffa3ef5

Parents:

991779c5

Message:

Replace old u?? types with respective C99 variants (e.g. uint32_t, int64_t, uintptr_t etc.).

File:

• arch/ia64/src/mm/tlb.c (modified) (19 diffs)

arch/ia64/src/mm/tlb.c

@@ -58 +58 @@
 {
                 ipl_t ipl;
-                __address adr;
-                __u32 count1, count2, stride1, stride2;
+                uintptr_t adr;
+                uint32_t count1, count2, stride1, stride2;
                 
                 int i,j;
@@ -102 +102 @@
 
 
-void tlb_invalidate_pages(asid_t asid, __address page, count_t cnt)
+void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt)
 {
         region_register rr;
@@ -109 +109 @@
         int c = cnt;
 
-        __address va;
+        uintptr_t va;
         va = page;
 
@@ -130 +130 @@
                 b++;
         b >>= 1;
-        __u64 ps;
+        uint64_t ps;
         
         switch (b) {
@@ -202 +202 @@
  * @param entry The rest of TLB entry as required by TLB insertion format.
  */
-void dtc_mapping_insert(__address va, asid_t asid, tlb_entry_t entry)
+void dtc_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry)
 {
         tc_mapping_insert(va, asid, entry, true);
@@ -213 +213 @@
  * @param entry The rest of TLB entry as required by TLB insertion format.
  */
-void itc_mapping_insert(__address va, asid_t asid, tlb_entry_t entry)
+void itc_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry)
 {
         tc_mapping_insert(va, asid, entry, false);
@@ -225 +225 @@
  * @param dtc If true, insert into data translation cache, use instruction translation cache otherwise.
  */
-void tc_mapping_insert(__address va, asid_t asid, tlb_entry_t entry, bool dtc)
+void tc_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, bool dtc)
 {
         region_register rr;
@@ -276 +276 @@
  * @param tr Translation register.
  */
-void itr_mapping_insert(__address va, asid_t asid, tlb_entry_t entry, index_t tr)
+void itr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, index_t tr)
 {
         tr_mapping_insert(va, asid, entry, false, tr);
@@ -288 +288 @@
  * @param tr Translation register.
  */
-void dtr_mapping_insert(__address va, asid_t asid, tlb_entry_t entry, index_t tr)
+void dtr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, index_t tr)
 {
         tr_mapping_insert(va, asid, entry, true, tr);
@@ -301 +301 @@
  * @param tr Translation register.
  */
-void tr_mapping_insert(__address va, asid_t asid, tlb_entry_t entry, bool dtr, index_t tr)
+void tr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, bool dtr, index_t tr)
 {
         region_register rr;
@@ -352 +352 @@
  * @param tr Translation register if dtr is true, ignored otherwise.
  */
-void dtlb_kernel_mapping_insert(__address page, __address frame, bool dtr, index_t tr)
+void dtlb_kernel_mapping_insert(uintptr_t page, uintptr_t frame, bool dtr, index_t tr)
 {
         tlb_entry_t entry;
@@ -381 +381 @@
  * @param width Width of the purge in bits.
  */
-void dtr_purge(__address page, count_t width)
+void dtr_purge(uintptr_t page, count_t width)
 {
         __asm__ volatile ("ptr.d %0, %1\n" : : "r" (page), "r" (width<<2));
@@ -445 +445 @@
  * @param istate Structure with saved interruption state.
  */
-void alternate_instruction_tlb_fault(__u64 vector, istate_t *istate)
+void alternate_instruction_tlb_fault(uint64_t vector, istate_t *istate)
 {
         region_register rr;
         rid_t rid;
-        __address va;
+        uintptr_t va;
         pte_t *t;
         
@@ -482 +482 @@
  * @param istate Structure with saved interruption state.
  */
-void alternate_data_tlb_fault(__u64 vector, istate_t *istate)
+void alternate_data_tlb_fault(uint64_t vector, istate_t *istate)
 {
         region_register rr;
         rid_t rid;
-        __address va;
+        uintptr_t va;
         pte_t *t;
         
@@ -531 +531 @@
  * @param istate Structure with saved interruption state.
  */
-void data_nested_tlb_fault(__u64 vector, istate_t *istate)
+void data_nested_tlb_fault(uint64_t vector, istate_t *istate)
 {
         panic("%s\n", __FUNCTION__);
@@ -541 +541 @@
  * @param istate Structure with saved interruption state.
  */
-void data_dirty_bit_fault(__u64 vector, istate_t *istate)
+void data_dirty_bit_fault(uint64_t vector, istate_t *istate)
 {
         region_register rr;
         rid_t rid;
-        __address va;
+        uintptr_t va;
         pte_t *t;
         
@@ -578 +578 @@
  * @param istate Structure with saved interruption state.
  */
-void instruction_access_bit_fault(__u64 vector, istate_t *istate)
+void instruction_access_bit_fault(uint64_t vector, istate_t *istate)
 {
         region_register rr;
         rid_t rid;
-        __address va;
+        uintptr_t va;
         pte_t *t;       
 
@@ -615 +615 @@
  * @param istate Structure with saved interruption state.
  */
-void data_access_bit_fault(__u64 vector, istate_t *istate)
+void data_access_bit_fault(uint64_t vector, istate_t *istate)
 {
         region_register rr;
         rid_t rid;
-        __address va;
+        uintptr_t va;
         pte_t *t;
 
@@ -652 +652 @@
  * @param istate Structure with saved interruption state.
  */
-void page_not_present(__u64 vector, istate_t *istate)
+void page_not_present(uint64_t vector, istate_t *istate)
 {
         region_register rr;
         rid_t rid;
-        __address va;
+        uintptr_t va;
         pte_t *t;