Changeset 8262010 in mainline for arch/ia32/src/smp/apic.c
- Timestamp:
- 2005-04-10T16:36:45Z (20 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 23c0c08
- Parents:
- 43114c5
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
arch/ia32/src/smp/apic.c
r43114c5 r8262010 27 27 */ 28 28 29 #ifdef __SMP__30 31 29 #include <arch/types.h> 32 30 #include <arch/smp/apic.h> … … 39 37 #include <arch/asm.h> 40 38 #include <arch.h> 39 40 #ifdef __SMP__ 41 41 42 42 /* … … 222 222 { 223 223 __u32 tmp, t1, t2; 224 224 int cpu_id = config.cpu_active - 1; 225 226 227 /* 228 * Here we set local APIC ID's so that they match operating system's CPU ID's 229 * This operation is dangerous as it is model specific. 230 * TODO: some care should be taken. 231 * NOTE: CPU may not be used to define APIC ID 232 */ 233 if (l_apic_id() != cpu_id) { 234 l_apic[L_APIC_ID] &= L_APIC_IDClear; 235 l_apic[L_APIC_ID] |= (l_apic[L_APIC_ID]&L_APIC_IDClear)|((cpu_id)<<L_APIC_IDShift); 236 } 225 237 226 238 l_apic[LVT_Err] |= (1<<16); … … 271 283 int i, lint; 272 284 273 printf("LVT on cpu%d, LAPIC ID: %d\n", CPU->id, (l_apic[L_APIC_ID] >> 24)&0xf);285 printf("LVT on cpu%d, LAPIC ID: %d\n", CPU->id, l_apic_id()); 274 286 275 287 printf("LVT_Tm: "); … … 305 317 * This register is supported only on P6 and higher. 306 318 */ 307 if (CPU-> family > 5) {319 if (CPU->arch.family > 5) { 308 320 printf("LVT_PCINT: "); 309 321 if (l_apic[LVT_PCINT] & (1<<16)) printf("masked"); else printf("not masked"); putchar(','); … … 324 336 l_apic_eoi(); 325 337 clock(); 338 } 339 340 __u8 l_apic_id(void) 341 { 342 return (l_apic[L_APIC_ID] >> L_APIC_IDShift)&L_APIC_IDMask; 326 343 } 327 344
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