Changeset 83742a4 in mainline for boot/arch/arm32/src/asm.S

Timestamp:

2013-01-20T16:02:33Z (12 years ago)

Author:

Jan Vesely <jano.vesely@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

b8bb2bc

Parents:

4a79e6f

Message:

arm32: Add cache maintenance to jump_to_kernel, enable caches on bbxm boot.

BBXM boots significantly faster.
Should be generic enough for all ARMs.

File:

• boot/arch/arm32/src/asm.S (modified) (1 diff)

boot/arch/arm32/src/asm.S

@@ -61 +61 @@
         #
 
+        #
+        # r0 is kernel entry point
+        # r1 is pointer to the bootinfo structure
+        # r2 is a kernel text end
+
+        # make sure kernel is flushed and available in memory
+        # Disable I-cache and D-cache before the kernel is started.
+        # TODO disabling DCache should not be necessary...
+#define CP15_C1_IC              12
+#define CP15_C1_DC              2
+        mrc     p15, 0, r4, c1, c0, 0
+        bic     r4, r4, #(1 << CP15_C1_DC)
+        bic     r4, r4, #(1 << CP15_C1_IC)
+        mcr     p15, 0, r4, c1, c0, 0
+
+        # use r4 as a moving pointer
+        mov r4, r0
+3:
+        # DCCMVAC (flush by virt address, to the point of coherence)
+        mcr p15, 0, r4, c7, c10, 1
+        # TODO: it would be better to use cacheline size
+        add r4, r4, #4
+        # are we there yet?
+        cmp r4, r2
+        blt 3b
+        nop
+        mov r4, #0
+        
+        #Wait for the operations to complete
+#ifdef PROCESSOR_ARCH_armv7_a
+        dsb
+#else
+        #cp15 dsb, r4 is ignored (should be zero)
+        mcr p15, 0, r4, c7, c10, 4
+#endif
+        
+        # Clean ICache and BPredictors, r4 ignored (SBZ)
+        mcr p15, 0, r4, c7, c5, 0
+
+        #Wait for the operations to complete
+#ifdef PROCESSOR_ARCH_armv7_a
+        isb
+#else
+        # cp15 isb
+        mcr p15, 0, r4, c7, c5, 4
+#endif
+        
+
 #if defined(MACHINE_gta02)