Changeset 89298e3 in mainline
- Timestamp:
- 2006-02-08T20:45:14Z (19 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 42744880
- Parents:
- bc78c75
- Location:
- arch/ia64
- Files:
-
- 3 edited
Legend:
- Unmodified
- Added
- Removed
-
arch/ia64/include/mm/page.h
rbc78c75 r89298e3 140 140 } vhpt_entry_t; 141 141 142 typedef vhpt_entry_t tlb_entry_t; 143 142 144 struct region_register_map { 143 145 unsigned ve : 1; … … 230 232 __asm__ volatile ( 231 233 "mov rr[%0] = %1;;\n" 232 "srlz.d;;\n"233 234 : 234 235 : "r" (i), "r" (v)); -
arch/ia64/include/mm/tlb.h
rbc78c75 r89298e3 42 42 void tlb_fill_code(__address va,asid_t asid,vhpt_entry_t entry); 43 43 44 void tlb_fill_code_tr(__u64 tr,__address va,asid_t asid,tlb_entry_t entry); 45 void tlb_fill_data_tr(__u64 tr,__address va,asid_t asid,tlb_entry_t entry); 46 47 44 48 45 49 #endif -
arch/ia64/src/mm/tlb.c
rbc78c75 r89298e3 33 33 #include <mm/tlb.h> 34 34 #include <arch/mm/tlb.h> 35 #include <arch/barrier.h> 35 36 36 37 … … 52 53 53 54 54 void tlb_fill_data(__address va,asid_t asid, vhpt_entry_t entry)55 { 56 region_register rr; 57 58 59 if(!(entry.not_present.p)) return; 60 61 rr.word=rr_read(VA_REGION(va)); 62 63 if(rr.map.rid==ASID2RID(asid,VA_REGION(va))) 64 { 65 asm 66 ( 67 "srlz.i;;\n" 68 "srlz.d;;\n" 69 "mov r8=psr;;\n" 70 "and r9=r8,%0;;\n" /*(~PSR_IC_MASK)*/ 71 "mov psr.l=r9;;\n" 72 "srlz.d;;\n" 73 "srlz.i;;\n" 74 "mov cr 20=%1\n" /*va*/ /*cr20 == IFA*/75 "mov cr 21=%2;;\n" /*entry.word[1]*/ /*cr21=ITIR*/55 void tlb_fill_data(__address va,asid_t asid,tlb_entry_t entry) 56 { 57 region_register rr; 58 59 60 if(!(entry.not_present.p)) return; 61 62 rr.word=rr_read(VA_REGION(va)); 63 64 if(rr.map.rid==ASID2RID(asid,VA_REGION(va))) 65 { 66 asm volatile 67 ( 68 "srlz.i;;\n" 69 "srlz.d;;\n" 70 "mov r8=psr;;\n" 71 "and r9=r8,%0;;\n" /*(~PSR_IC_MASK)*/ 72 "mov psr.l=r9;;\n" 73 "srlz.d;;\n" 74 "srlz.i;;\n" 75 "mov cr.ifa=%1\n" /*va*/ 76 "mov cr.itir=%2;;\n" /*entry.word[1]*/ 76 77 "itc.d %3;;\n" /*entry.word[0]*/ 77 78 "mov psr.l=r8;;\n" … … 88 89 rr0.map.rid=ASID2RID(asid,VA_REGION(va)); 89 90 rr_write(VA_REGION(va),rr0.word); 90 asm 91 ( 92 "mov r8=psr;;\n" 93 "and r9=r8,%0;;\n" /*(~PSR_IC_MASK)*/ 94 "mov psr.l=r9;;\n" 95 "srlz.d;;\n" 96 "mov cr20=%1\n" /*va*/ /*cr20 == IFA*/ 97 "mov cr21=%2;;\n" /*entry.word[1]*/ /*cr21=ITIR*/ 91 srlz_d(); 92 asm volatile 93 ( 94 "mov r8=psr;;\n" 95 "and r9=r8,%0;;\n" /*(~PSR_IC_MASK)*/ 96 "mov psr.l=r9;;\n" 97 "srlz.d;;\n" 98 "mov cr.ifa=%1\n" /*va*/ 99 "mov cr.itir=%2;;\n" /*entry.word[1]*/ 98 100 "itc.d %3;;\n" /*entry.word[0]*/ 99 101 "mov psr.l=r8;;\n" … … 109 111 } 110 112 111 void tlb_fill_code(__address va,asid_t asid, vhpt_entry_t entry)112 { 113 region_register rr; 114 115 116 if(!(entry.not_present.p)) return; 117 118 rr.word=rr_read(VA_REGION(va)); 119 120 if(rr.map.rid==ASID2RID(asid,VA_REGION(va))) 121 { 122 asm 123 ( 124 "srlz.i;;\n" 125 "srlz.d;;\n" 126 "mov r8=psr;;\n" 127 "and r9=r8,%0;;\n" /*(~PSR_IC_MASK)*/ 128 "mov psr.l=r9;;\n" 129 "srlz.d;;\n" 130 "srlz.i;;\n" 131 "mov cr 20=%1\n" /*va*/ /*cr20 == IFA*/132 "mov cr 21=%2;;\n" /*entry.word[1]*/ /*cr21=ITIR*/113 void tlb_fill_code(__address va,asid_t asid,tlb_entry_t entry) 114 { 115 region_register rr; 116 117 118 if(!(entry.not_present.p)) return; 119 120 rr.word=rr_read(VA_REGION(va)); 121 122 if(rr.map.rid==ASID2RID(asid,VA_REGION(va))) 123 { 124 asm volatile 125 ( 126 "srlz.i;;\n" 127 "srlz.d;;\n" 128 "mov r8=psr;;\n" 129 "and r9=r8,%0;;\n" /*(~PSR_IC_MASK)*/ 130 "mov psr.l=r9;;\n" 131 "srlz.d;;\n" 132 "srlz.i;;\n" 133 "mov cr.ifa=%1\n" /*va*/ 134 "mov cr.itir=%2;;\n" /*entry.word[1]*/ 133 135 "itc.i %3;;\n" /*entry.word[0]*/ 134 136 "mov psr.l=r8;;\n" … … 145 147 rr0.map.rid=ASID2RID(asid,VA_REGION(va)); 146 148 rr_write(VA_REGION(va),rr0.word); 147 asm 148 ( 149 "mov r8=psr;;\n" 150 "and r9=r8,%0;;\n" /*(~PSR_IC_MASK)*/ 151 "mov psr.l=r9;;\n" 152 "srlz.d;;\n" 153 "mov cr20=%1\n" /*va*/ /*cr20 == IFA*/ 154 "mov cr21=%2;;\n" /*entry.word[1]*/ /*cr21=ITIR*/ 149 srlz_d(); 150 asm volatile 151 ( 152 "mov r8=psr;;\n" 153 "and r9=r8,%0;;\n" /*(~PSR_IC_MASK)*/ 154 "mov psr.l=r9;;\n" 155 "srlz.d;;\n" 156 "mov cr.ifa=%1\n" /*va*/ 157 "mov cr.itir=%2;;\n" /*entry.word[1]*/ 155 158 "itc.i %3;;\n" /*entry.word[0]*/ 156 159 "mov psr.l=r8;;\n" … … 167 170 168 171 172 void tlb_fill_data_tr(__u64 tr,__address va,asid_t asid,tlb_entry_t entry) 173 { 174 region_register rr; 175 176 177 if(!(entry.not_present.p)) return; 178 179 rr.word=rr_read(VA_REGION(va)); 180 181 if(rr.map.rid==ASID2RID(asid,VA_REGION(va))) 182 { 183 asm volatile 184 ( 185 "srlz.i;;\n" 186 "srlz.d;;\n" 187 "mov r8=psr;;\n" 188 "and r9=r8,%0;;\n" /*(~PSR_IC_MASK)*/ 189 "mov psr.l=r9;;\n" 190 "srlz.d;;\n" 191 "srlz.i;;\n" 192 "mov cr.ifa=%1\n" /*va*/ 193 "mov cr.itir=%2;;\n" /*entry.word[1]*/ 194 "itr.d dtr[%4]=%3;;\n" /*entry.word[0]*/ 195 "mov psr.l=r8;;\n" 196 "srlz.d;;\n" 197 : 198 :"r"(~PSR_IC_MASK),"r"(va),"r"(entry.word[1]),"r"(entry.word[0]),"r"(tr) 199 :"r8","r9" 200 ); 201 } 202 else 203 { 204 region_register rr0; 205 rr0=rr; 206 rr0.map.rid=ASID2RID(asid,VA_REGION(va)); 207 rr_write(VA_REGION(va),rr0.word); 208 srlz_d(); 209 asm volatile 210 ( 211 "mov r8=psr;;\n" 212 "and r9=r8,%0;;\n" /*(~PSR_IC_MASK)*/ 213 "mov psr.l=r9;;\n" 214 "srlz.d;;\n" 215 "mov cr.ifa=%1\n" /*va*/ 216 "mov cr.itir=%2;;\n" /*entry.word[1]*/ 217 "itr.d dtr[%4]=%3;;\n" /*entry.word[0]*/ 218 "mov psr.l=r8;;\n" 219 "srlz.d;;\n" 220 : 221 :"r"(~PSR_IC_MASK),"r"(va),"r"(entry.word[1]),"r"(entry.word[0]),"r"(tr) 222 :"r8","r9" 223 ); 224 rr_write(VA_REGION(va),rr.word); 225 } 226 227 228 } 229 230 void tlb_fill_code_tr(__u64 tr,__address va,asid_t asid,tlb_entry_t entry) 231 { 232 region_register rr; 233 234 235 if(!(entry.not_present.p)) return; 236 237 rr.word=rr_read(VA_REGION(va)); 238 239 if(rr.map.rid==ASID2RID(asid,VA_REGION(va))) 240 { 241 asm volatile 242 ( 243 "srlz.i;;\n" 244 "srlz.d;;\n" 245 "mov r8=psr;;\n" 246 "and r9=r8,%0;;\n" /*(~PSR_IC_MASK)*/ 247 "mov psr.l=r9;;\n" 248 "srlz.d;;\n" 249 "srlz.i;;\n" 250 "mov cr.ifa=%1\n" /*va*/ 251 "mov cr.itir=%2;;\n" /*entry.word[1]*/ 252 "itr.i itr[%4]=%3;;\n" /*entry.word[0]*/ 253 "mov psr.l=r8;;\n" 254 "srlz.d;;\n" 255 : 256 :"r"(~PSR_IC_MASK),"r"(va),"r"(entry.word[1]),"r"(entry.word[0]),"r"(tr) 257 :"r8","r9" 258 ); 259 } 260 else 261 { 262 region_register rr0; 263 rr0=rr; 264 rr0.map.rid=ASID2RID(asid,VA_REGION(va)); 265 rr_write(VA_REGION(va),rr0.word); 266 srlz_d(); 267 asm volatile 268 ( 269 "mov r8=psr;;\n" 270 "and r9=r8,%0;;\n" /*(~PSR_IC_MASK)*/ 271 "mov psr.l=r9;;\n" 272 "srlz.d;;\n" 273 "mov cr.ifa=%1\n" /*va*/ 274 "mov cr.itir=%2;;\n" /*entry.word[1]*/ 275 "itr.i itr[%4]=%3;;\n" /*entry.word[0]*/ 276 "mov psr.l=r8;;\n" 277 "srlz.d;;\n" 278 : 279 :"r"(~PSR_IC_MASK),"r"(va),"r"(entry.word[1]),"r"(entry.word[0]),"r"(tr) 280 :"r8","r9" 281 ); 282 rr_write(VA_REGION(va),rr.word); 283 } 284 285 286 } 287
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