Changeset bc78c75 in mainline

Timestamp:

2006-02-08T17:15:56Z (19 years ago)

Author:

Jakub Vana <jakub.vana@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

89298e3

Parents:

4c8715d2

Message:

IA-64 TLB filling functions for dynamic tlb filling (TC tlb).

Location:

arch/ia64

Files:

• include/mm/page.h (modified) (2 diffs)
• include/mm/tlb.h (modified) (1 diff)
• src/mm/tlb.c (modified) (2 diffs)

arch/ia64/include/mm/page.h

@@ -71 +71 @@
 #define AR_EXECUTE      0x1
 #define AR_WRITE        0x2
+
+
+#define VA_REGION_INDEX 61
+
+#define VA_REGION(va) (va>>VA_REGION_INDEX)
+
+
 
 struct vhpt_tag_info {
@@ -221 +228 @@
 {
         ASSERT(i < REGION_REGISTERS);
-        __asm__ volatile ("mov rr[%0] = %1\n" : : "r" (i), "r" (v));
+        __asm__ volatile (
+        "mov rr[%0] = %1;;\n" 
+        "srlz.d;;\n"
+        : 
+        : "r" (i), "r" (v));
 }
  

arch/ia64/include/mm/tlb.h

@@ -33 +33 @@
 #define tlb_print()
 
+
+#include <arch/mm/page.h>
+#include <arch/mm/asid.h>
+#include <arch/register.h>
+
+
+void tlb_fill_data(__address va,asid_t asid,vhpt_entry_t entry);
+void tlb_fill_code(__address va,asid_t asid,vhpt_entry_t entry);
+
+
 #endif
+
+

arch/ia64/src/mm/tlb.c

@@ -32 +32 @@
 
 #include <mm/tlb.h>
-#include <arch/mm/asid.h>
+#include <arch/mm/tlb.h>
+
 
 /** Invalidate all TLB entries. */
@@ -48 +49 @@
         /* TODO */
 }
+
+
+
+void tlb_fill_data(__address va,asid_t asid,vhpt_entry_t entry)
+{
+        region_register rr;
+
+
+        if(!(entry.not_present.p)) return;
+
+        rr.word=rr_read(VA_REGION(va));
+
+        if(rr.map.rid==ASID2RID(asid,VA_REGION(va)))
+        {
+                asm
+                (
+                        "srlz.i;;\n"
+                        "srlz.d;;\n"
+                        "mov r8=psr;;\n"
+                        "and r9=r8,%0;;\n"                              /*(~PSR_IC_MASK)*/
+                        "mov psr.l=r9;;\n"
+                        "srlz.d;;\n"
+                        "srlz.i;;\n"
+                        "mov cr20=%1\n"                 /*va*/          /*cr20 == IFA*/ 
+                        "mov cr21=%2;;\n"                                       /*entry.word[1]*/ /*cr21=ITIR*/
+                        "itc.d %3;;\n"                                          /*entry.word[0]*/
+                        "mov psr.l=r8;;\n"
+                        "srlz.d;;\n"
+                        :
+                        :"r"(~PSR_IC_MASK),"r"(va),"r"(entry.word[1]),"r"(entry.word[0])
+                        :"r8","r9"
+                );
+        }
+        else
+        {
+                region_register rr0;
+                rr0=rr;
+                rr0.map.rid=ASID2RID(asid,VA_REGION(va));
+                rr_write(VA_REGION(va),rr0.word);
+                asm
+                (
+                        "mov r8=psr;;\n"
+                        "and r9=r8,%0;;\n"                              /*(~PSR_IC_MASK)*/
+                        "mov psr.l=r9;;\n"
+                        "srlz.d;;\n"
+                        "mov cr20=%1\n"                 /*va*/          /*cr20 == IFA*/ 
+                        "mov cr21=%2;;\n"                                       /*entry.word[1]*/ /*cr21=ITIR*/
+                        "itc.d %3;;\n"                                          /*entry.word[0]*/
+                        "mov psr.l=r8;;\n"
+                        "srlz.d;;\n"
+                        :
+                        :"r"(~PSR_IC_MASK),"r"(va),"r"(entry.word[1]),"r"(entry.word[0])
+                        :"r8","r9"
+                );
+                rr_write(VA_REGION(va),rr.word);
+        }
+
+
+}
+
+void tlb_fill_code(__address va,asid_t asid,vhpt_entry_t entry)
+{
+        region_register rr;
+
+
+        if(!(entry.not_present.p)) return;
+
+        rr.word=rr_read(VA_REGION(va));
+
+        if(rr.map.rid==ASID2RID(asid,VA_REGION(va)))
+        {
+                asm
+                (
+                        "srlz.i;;\n"
+                        "srlz.d;;\n"
+                        "mov r8=psr;;\n"
+                        "and r9=r8,%0;;\n"                              /*(~PSR_IC_MASK)*/
+                        "mov psr.l=r9;;\n"
+                        "srlz.d;;\n"
+                        "srlz.i;;\n"
+                        "mov cr20=%1\n"                 /*va*/          /*cr20 == IFA*/ 
+                        "mov cr21=%2;;\n"                                       /*entry.word[1]*/ /*cr21=ITIR*/
+                        "itc.i %3;;\n"                                          /*entry.word[0]*/
+                        "mov psr.l=r8;;\n"
+                        "srlz.d;;\n"
+                        :
+                        :"r"(~PSR_IC_MASK),"r"(va),"r"(entry.word[1]),"r"(entry.word[0])
+                        :"r8","r9"
+                );
+        }
+        else
+        {
+                region_register rr0;
+                rr0=rr;
+                rr0.map.rid=ASID2RID(asid,VA_REGION(va));
+                rr_write(VA_REGION(va),rr0.word);
+                asm
+                (
+                        "mov r8=psr;;\n"
+                        "and r9=r8,%0;;\n"                              /*(~PSR_IC_MASK)*/
+                        "mov psr.l=r9;;\n"
+                        "srlz.d;;\n"
+                        "mov cr20=%1\n"                 /*va*/          /*cr20 == IFA*/ 
+                        "mov cr21=%2;;\n"                                       /*entry.word[1]*/ /*cr21=ITIR*/
+                        "itc.i %3;;\n"                                          /*entry.word[0]*/
+                        "mov psr.l=r8;;\n"
+                        "srlz.d;;\n"
+                        :
+                        :"r"(~PSR_IC_MASK),"r"(va),"r"(entry.word[1]),"r"(entry.word[0])
+                        :"r8","r9"
+                );
+                rr_write(VA_REGION(va),rr.word);
+        }
+
+
+}
+
+