Changeset 8f88beb in mainline for uspace/drv/infrastructure/rootamdm37x/cm/clock_control.h

Timestamp:

2012-11-25T21:34:07Z (12 years ago)

Author:

Maurizio Lombardi <m.lombardi85@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

e1a27be

Parents:

150a271 (diff), 7462674 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.

Message:

Merge mainline changes

File:

• uspace/drv/infrastructure/rootamdm37x/cm/clock_control.h (modified) (3 diffs)

uspace/drv/infrastructure/rootamdm37x/cm/clock_control.h

@@ -67 +67 @@
 
         ioport32_t clken2_pll;
-#define CLOCK_CONTROL_CM_CLKEN_PLL_EN_PERIPH2_DPLL_LPMODE_FLAG   (1 << 10)
-#define CLOCK_CONTROL_CM_CLKEN_PLL_EN_PERIPH2_DPLL_DRIFTGUARD_FLAG   (1 << 3)
-#define CLOCK_CONTROL_CM_CLKEN_PLL_EN_PERIPH2_DPLL_MASK   (0x7)
-#define CLOCK_CONTROL_CM_CLKEN_PLL_EN_PERIPH2_DPLL_LP_STOP   (0x1)
-#define CLOCK_CONTROL_CM_CLKEN_PLL_EN_PERIPH2_DPLL_LOCK   (0x7)
+#define CLOCK_CONTROL_CM_CLKEN2_PLL_EN_PERIPH2_DPLL_LPMODE_FLAG   (1 << 10)
+#define CLOCK_CONTROL_CM_CLKEN2_PLL_EN_PERIPH2_DPLL_DRIFTGUARD_FLAG   (1 << 3)
+#define CLOCK_CONTROL_CM_CLKEN2_PLL_EN_PERIPH2_DPLL_MASK   (0x7)
+#define CLOCK_CONTROL_CM_CLKEN2_PLL_EN_PERIPH2_DPLL_LP_STOP   (0x1)
+#define CLOCK_CONTROL_CM_CLKEN2_PLL_EN_PERIPH2_DPLL_LOCK   (0x7)
 
         PADD32[6];
@@ -114 +114 @@
         ioport32_t clksel1_pll;
 #define CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_CLKOUT_DIV_MASK   (0x1f << 27)
-#define CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_CLKOUT_DIV_(x)   (((x) & 0x1f) << 27)
+#define CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_CLKOUT_DIV_CREATE(x)   (((x) & 0x1f) << 27)
+#define CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_CLKOUT_DIV_GET(x)   (((x) >> 27) & 0x1f)
 #define CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_MULT_MASK   (0x7ff << 16)
-#define CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_MULT(x)   (((x) & 0x7ff) << 16)
+#define CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_MULT_CREATE(x)   (((x) & 0x7ff) << 16)
+#define CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_MULT_GET(x)   (((x) >> 16) & 0x7ff)
 #define CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_DIV_MASK   (0x7f << 8)
-#define CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_DIV(x)   (((x) & 0x7f) << 8)
+#define CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_DIV_CREATE(x)   (((x) & 0x7f) << 8)
+#define CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_DIV_GET(x)   (((x) >> 8) & 0x7f)
 #define CLOCK_CONTROL_CM_CLKSEL1_PLL_SOURCE_96M_FLAG   (1 << 6)
 #define CLOCK_CONTROL_CM_CLKSEL1_PLL_SOURCE_54M_FLAG   (1 << 5)
@@ -140 +143 @@
         ioport32_t clksel4_pll;
 #define CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_MULT_MASK   (0x7ff << 8)
-#define CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_MULT(x)   (((x) & 0x7ff) << 8)
+#define CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_MULT_CREATE(x)   (((x) & 0x7ff) << 8)
+#define CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_MULT_GET(x)   (((x) >> 8) & 0x7ff)
 #define CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_DIV_MASK   (0x7f)
-#define CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_DIV(x)   ((x) & 0x7f)
+#define CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_DIV_CREATE(x)   ((x) & 0x7f)
+#define CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_DIV_GET(x)   ((x) & 0x7f)
 
         ioport32_t clksel5_pll;
 #define CLOCK_CONTROL_CM_CLKSEL5_PLL_DIV120M_MASK   (0x1f)
-#define CLOCK_CONTROL_CM_CLKSEL5_PLL_DIV120M(x)   ((x) & 0x1f)
+#define CLOCK_CONTROL_CM_CLKSEL5_PLL_DIV120M_CREATE(x)   ((x) & 0x1f)
+#define CLOCK_CONTROL_CM_CLKSEL5_PLL_DIV120M_GET(x)   ((x) & 0x1f)
 } clock_control_cm_regs_t;