Changeset 93fb170c in mainline for uspace/srv/hw/netif/dp8390/dp8390.h


Ignore:
Timestamp:
2011-01-08T18:51:31Z (14 years ago)
Author:
Jan Vesely <jano.vesely@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
15be932
Parents:
8f748215 (diff), a523af4 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.
Message:

Merge from main branch

File:
1 edited

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  • uspace/srv/hw/netif/dp8390/dp8390.h

    r8f748215 r93fb170c  
    11/*
    2  * Copyright (c) 1987,1997, 2006, Vrije Universiteit, Amsterdam, The Netherlands All rights reserved. Redistribution and use of the MINIX 3 operating system in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
    3  *
    4  * * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
    5  * * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
    6  * * Neither the name of the Vrije Universiteit nor the names of the software authors or contributors may be used to endorse or promote products derived from this software without specific prior written permission.
    7  * * Any deviations from these conditions require written permission from the copyright holder in advance
    8  *
    9  *
    10  * Disclaimer
    11  *
    12  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS, AUTHORS, AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR
     2 * Copyright (c) 2009 Lukas Mejdrech
     3 * Copyright (c) 2011 Martin Decky
     4 * All rights reserved.
     5 *
     6 * Redistribution and use in source and binary forms, with or without
     7 * modification, are permitted provided that the following conditions
     8 * are met:
     9 *
     10 * - Redistributions of source code must retain the above copyright
     11 *   notice, this list of conditions and the following disclaimer.
     12 * - Redistributions in binary form must reproduce the above copyright
     13 *   notice, this list of conditions and the following disclaimer in the
     14 *   documentation and/or other materials provided with the distribution.
     15 * - The name of the author may not be used to endorse or promote products
     16 *   derived from this software without specific prior written permission.
     17 *
     18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
    1319 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
    1420 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
    15  * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR ANY AUTHORS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
     21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
    1622 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
    1723 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
    … …  
    2026 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
    2127 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
    22  *
    23  * Changes:
    24  *  2009 ported to HelenOS, Lukas Mejdrech
     28 */
     29
     30/*
     31 * This code is based upon the NE2000 driver for MINIX,
     32 * distributed according to a BSD-style license.
     33 *
     34 * Copyright (c) 1987, 1997, 2006 Vrije Universiteit
     35 * Copyright (c) 1992, 1994 Philip Homburg
     36 * Copyright (c) 1996 G. Falzoni
     37 *
    2538 */
    2639
    … …  
    3750
    3851#include <net/packet.h>
    39 
    4052#include "dp8390_port.h"
    41 #include "local.h"
    42 
    43 /** Input/output size.
    44  */
    45 #define DP8390_IO_SIZE  0x020
    46 
    47 /*
    48 dp8390.h
    49 
    50 Created:        before Dec 28, 1992 by Philip Homburg
    51 */
     53
     54/** Input/output size */
     55#define DP8390_IO_SIZE  0x0020
    5256
    5357/* National Semiconductor DP8390 Network Interface Controller. */
    5458
    55                                 /* Page 0, for reading ------------- */
    56 #define DP_CR           0x0     /* Read side of Command Register     */
    57 #define DP_CLDA0        0x1     /* Current Local Dma Address 0       */
    58 #define DP_CLDA1        0x2     /* Current Local Dma Address 1       */
    59 #define DP_BNRY         0x3     /* Boundary Pointer                  */
    60 #define DP_TSR          0x4     /* Transmit Status Register          */
    61 #define DP_NCR          0x5     /* Number of Collisions Register     */
    62 #define DP_FIFO         0x6     /* Fifo ??                           */
    63 #define DP_ISR          0x7     /* Interrupt Status Register         */
    64 #define DP_CRDA0        0x8     /* Current Remote Dma Address 0      */
    65 #define DP_CRDA1        0x9     /* Current Remote Dma Address 1      */
    66 #define DP_DUM1         0xA     /* unused                            */
    67 #define DP_DUM2         0xB     /* unused                            */
    68 #define DP_RSR          0xC     /* Receive Status Register           */
    69 #define DP_CNTR0        0xD     /* Tally Counter 0                   */
    70 #define DP_CNTR1        0xE     /* Tally Counter 1                   */
    71 #define DP_CNTR2        0xF     /* Tally Counter 2                   */
    72 
    73                                 /* Page 0, for writing ------------- */
    74 #define DP_CR           0x0     /* Write side of Command Register    */
    75 #define DP_PSTART       0x1     /* Page Start Register               */
    76 #define DP_PSTOP        0x2     /* Page Stop Register                */
    77 #define DP_BNRY         0x3     /* Boundary Pointer                  */
    78 #define DP_TPSR         0x4     /* Transmit Page Start Register      */
    79 #define DP_TBCR0        0x5     /* Transmit Byte Count Register 0    */
    80 #define DP_TBCR1        0x6     /* Transmit Byte Count Register 1    */
    81 #define DP_ISR          0x7     /* Interrupt Status Register         */
    82 #define DP_RSAR0        0x8     /* Remote Start Address Register 0   */
    83 #define DP_RSAR1        0x9     /* Remote Start Address Register 1   */
    84 #define DP_RBCR0        0xA     /* Remote Byte Count Register 0      */
    85 #define DP_RBCR1        0xB     /* Remote Byte Count Register 1      */
    86 #define DP_RCR          0xC     /* Receive Configuration Register    */
    87 #define DP_TCR          0xD     /* Transmit Configuration Register   */
    88 #define DP_DCR          0xE     /* Data Configuration Register       */
    89 #define DP_IMR          0xF     /* Interrupt Mask Register           */
    90 
    91                                 /* Page 1, read/write -------------- */
    92 #define DP_CR           0x0     /* Command Register                  */
    93 #define DP_PAR0         0x1     /* Physical Address Register 0       */
    94 #define DP_PAR1         0x2     /* Physical Address Register 1       */
    95 #define DP_PAR2         0x3     /* Physical Address Register 2       */
    96 #define DP_PAR3         0x4     /* Physical Address Register 3       */
    97 #define DP_PAR4         0x5     /* Physical Address Register 4       */
    98 #define DP_PAR5         0x6     /* Physical Address Register 5       */
    99 #define DP_CURR         0x7     /* Current Page Register             */
    100 #define DP_MAR0         0x8     /* Multicast Address Register 0      */
    101 #define DP_MAR1         0x9     /* Multicast Address Register 1      */
    102 #define DP_MAR2         0xA     /* Multicast Address Register 2      */
    103 #define DP_MAR3         0xB     /* Multicast Address Register 3      */
    104 #define DP_MAR4         0xC     /* Multicast Address Register 4      */
    105 #define DP_MAR5         0xD     /* Multicast Address Register 5      */
    106 #define DP_MAR6         0xE     /* Multicast Address Register 6      */
    107 #define DP_MAR7         0xF     /* Multicast Address Register 7      */
     59/** Page 0, for reading */
     60#define DP_CR     0x00  /**< Command Register */
     61#define DP_CLDA0  0x01  /**< Current Local DMA Address 0 */
     62#define DP_CLDA1  0x02  /**< Current Local DMA Address 1 */
     63#define DP_BNRY   0x03  /**< Boundary Pointer */
     64#define DP_TSR    0x04  /**< Transmit Status Register */
     65#define DP_NCR    0x05  /**< Number of Collisions Register */
     66#define DP_FIFO   0x06  /**< FIFO */
     67#define DP_ISR    0x07  /**< Interrupt Status Register */
     68#define DP_CRDA0  0x08  /**< Current Remote DMA Address 0 */
     69#define DP_CRDA1  0x09  /**< Current Remote DMA Address 1 */
     70#define DP_RSR    0x0c  /**< Receive Status Register */
     71#define DP_CNTR0  0x0d  /**< Tally Counter 0 */
     72#define DP_CNTR1  0x0e  /**< Tally Counter 1 */
     73#define DP_CNTR2  0x0f  /**< Tally Counter 2 */
     74
     75/** Page 0, for writing */
     76#define DP_PSTART  0x01  /**< Page Start Register*/
     77#define DP_PSTOP   0x02  /**< Page Stop Register */
     78#define DP_TPSR    0x04  /**< Transmit Page Start Register */
     79#define DP_TBCR0   0x05  /**< Transmit Byte Count Register 0 */
     80#define DP_TBCR1   0x06  /**< Transmit Byte Count Register 1 */
     81#define DP_RSAR0   0x08  /**< Remote Start Address Register 0 */
     82#define DP_RSAR1   0x09  /**< Remote Start Address Register 1 */
     83#define DP_RBCR0   0x0a  /**< Remote Byte Count Register 0 */
     84#define DP_RBCR1   0x0b  /**< Remote Byte Count Register 1 */
     85#define DP_RCR     0x0c  /**< Receive Configuration Register */
     86#define DP_TCR     0x0d  /**< Transmit Configuration Register */
     87#define DP_DCR     0x0e  /**< Data Configuration Register */
     88#define DP_IMR     0x0f  /**< Interrupt Mask Register */
     89
     90/** Page 1, read/write */
     91#define DP_PAR0  0x01  /**< Physical Address Register 0 */
     92#define DP_PAR1  0x02  /**< Physical Address Register 1 */
     93#define DP_PAR2  0x03  /**< Physical Address Register 2 */
     94#define DP_PAR3  0x04  /**< Physical Address Register 3 */
     95#define DP_PAR4  0x05  /**< Physical Address Register 4 */
     96#define DP_PAR5  0x06  /**< Physical Address Register 5 */
     97#define DP_CURR  0x07  /**< Current Page Register */
     98#define DP_MAR0  0x08  /**< Multicast Address Register 0 */
     99#define DP_MAR1  0x09  /**< Multicast Address Register 1 */
     100#define DP_MAR2  0x0a  /**< Multicast Address Register 2 */
     101#define DP_MAR3  0x0b  /**< Multicast Address Register 3 */
     102#define DP_MAR4  0x0c  /**< Multicast Address Register 4 */
     103#define DP_MAR5  0x0d  /**< Multicast Address Register 5 */
     104#define DP_MAR6  0x0e  /**< Multicast Address Register 6 */
     105#define DP_MAR7  0x0f  /**< Multicast Address Register 7 */
    108106
    109107/* Bits in dp_cr */
    … …  
    199197#define RSR_DFR         0x80    /* In later manuals: Deferring       */
    200198
    201 /** Type definition of the receive header.
    202  */
    203 typedef struct dp_rcvhdr
    204 {
    205         /** Copy of rsr.
    206          */
    207         u8_t dr_status;
    208         /** Pointer to next packet.
    209          */
    210         u8_t dr_next;
    211         /** Receive Byte Count Low.
    212          */
    213         u8_t dr_rbcl;
    214         /** Receive Byte Count High.
    215          */
    216         u8_t dr_rbch;
     199/** Type definition of the receive header
     200 *
     201 */
     202typedef struct dp_rcvhdr {
     203        /** Copy of rsr */
     204        uint8_t dr_status;
     205       
     206        /** Pointer to next packet */
     207        uint8_t dr_next;
     208       
     209        /** Receive Byte Count Low */
     210        uint8_t dr_rbcl;
     211       
     212        /** Receive Byte Count High */
     213        uint8_t dr_rbch;
    217214} dp_rcvhdr_t;
    218215
    219 /** Page size.
    220  */
    221 #define DP_PAGESIZE     256
    222 
    223 /* Some macros to simplify accessing the dp8390 */
    224 /** Reads 1 byte from the zero page register.
     216/** Page size */
     217#define DP_PAGESIZE  256
     218
     219/** Read 1 byte from the zero page register.
    225220 *  @param[in] dep The network interface structure.
    226221 *  @param[in] reg The register offset.
    227222 *  @returns The read value.
    228223 */
    229 #define inb_reg0(dep, reg)              (inb(dep->de_dp8390_port+reg))
    230 
    231 /** Writes 1 byte zero page register.
     224#define inb_reg0(dep, reg)  (inb(dep->de_dp8390_port + reg))
     225
     226/** Write 1 byte zero page register.
    232227 *  @param[in] dep The network interface structure.
    233228 *  @param[in] reg The register offset.
    234229 *  @param[in] data The value to be written.
    235230 */
    236 #define outb_reg0(dep, reg, data)       (outb(dep->de_dp8390_port+reg, data))
    237 
    238 /** Reads 1 byte from the first page register.
     231#define outb_reg0(dep, reg, data)  (outb(dep->de_dp8390_port + reg, data))
     232
     233/** Read 1 byte from the first page register.
    239234 *  @param[in] dep The network interface structure.
    240235 *  @param[in] reg The register offset.
    241236 *  @returns The read value.
    242237 */
    243 #define inb_reg1(dep, reg)              (inb(dep->de_dp8390_port+reg))
    244 
    245 /** Writes 1 byte first page register.
     238#define inb_reg1(dep, reg)  (inb(dep->de_dp8390_port + reg))
     239
     240/** Write 1 byte first page register.
    246241 *  @param[in] dep The network interface structure.
    247242 *  @param[in] reg The register offset.
    248243 *  @param[in] data The value to be written.
    249244 */
    250 #define outb_reg1(dep, reg, data)       (outb(dep->de_dp8390_port+reg, data))
    251 
    252 /* Software interface to the dp8390 driver */
    253 
    254 struct dpeth;
    255 struct iovec_dat;
    256 //struct iovec_dat_s;
    257 _PROTOTYPE(typedef void (*dp_initf_t), (struct dpeth *dep)              );
    258 _PROTOTYPE(typedef void (*dp_stopf_t), (struct dpeth *dep)              );
    259 _PROTOTYPE(typedef void (*dp_user2nicf_t), (struct dpeth *dep,
    260                         struct iovec_dat *iovp, vir_bytes offset,
    261                         int nic_addr, vir_bytes count) );
    262 //_PROTOTYPE(typedef void (*dp_user2nicf_s_t), (struct dpeth *dep,
    263 //                      struct iovec_dat_s *iovp, vir_bytes offset,
    264 //                      int nic_addr, vir_bytes count)                  );
    265 _PROTOTYPE(typedef void (*dp_nic2userf_t), (struct dpeth *dep,
    266                         int nic_addr, struct iovec_dat *iovp,
    267                         vir_bytes offset, vir_bytes count) );
    268 //_PROTOTYPE(typedef void (*dp_nic2userf_s_t), (struct dpeth *dep,
    269 //                      int nic_addr, struct iovec_dat_s *iovp,
    270 //                      vir_bytes offset, vir_bytes count)              );
    271 //#if 0
    272 //_PROTOTYPE(typedef void (*dp_getheaderf_t), (struct dpeth *dep,
    273 //                      int page, struct dp_rcvhdr *h, u16_t *eth_type) );
    274 //#endif
    275 _PROTOTYPE(typedef void (*dp_getblock_t), (struct dpeth *dep,
    276                 int page, size_t offset, size_t size, void *dst)        );
    277 
    278 /* iovectors are handled IOVEC_NR entries at a time. */
    279 //#define IOVEC_NR      16
    280 // no vectors allowed
    281 #define IOVEC_NR        1
    282 
    283 /*
    284 typedef int irq_hook_t;
    285 */
    286 typedef struct iovec_dat
    287 {
    288   iovec_t iod_iovec[IOVEC_NR];
    289   int iod_iovec_s;
    290   // no direct process access
    291   int iod_proc_nr;
    292   vir_bytes iod_iovec_addr;
    293 } iovec_dat_t;
    294 /*
    295 typedef struct iovec_dat_s
    296 {
    297   iovec_s_t iod_iovec[IOVEC_NR];
    298   int iod_iovec_s;
    299   int iod_proc_nr;
    300   cp_grant_id_t iod_grant;
    301   vir_bytes iod_iovec_offset;
    302 } iovec_dat_s_t;
    303 */
    304 #define SENDQ_NR        1       /* Maximum size of the send queue */
    305 #define SENDQ_PAGES     6       /* 6 * DP_PAGESIZE >= 1514 bytes */
    306 
    307 /** Maximum number of waiting packets to be sent or received.
    308  */
    309 #define MAX_PACKETS     4
    310 
    311 typedef struct dpeth
    312 {
    313         /** Outgoing packets queue.
    314          */
    315         packet_t *packet_queue;
    316         /** Outgoing packets count.
    317          */
    318         int packet_count;
    319 
    320         /** Received packets queue.
    321          */
    322         packet_t *received_queue;
    323         /** Received packets count.
    324          */
    325         int received_count;
    326 
    327         /* The de_base_port field is the starting point of the probe.
    328          * The conf routine also fills de_linmem and de_irq. If the probe
     245#define outb_reg1(dep, reg, data)  (outb(dep->de_dp8390_port + reg, data))
     246
     247#define SENDQ_NR     2  /* Maximum size of the send queue */
     248#define SENDQ_PAGES  6  /* 6 * DP_PAGESIZE >= 1514 bytes */
     249
     250typedef struct dpeth {
     251        /*
     252         * The de_base_port field is the starting point of the probe.
     253         * The conf routine also fills de_irq. If the probe
    329254         * routine knows the irq and/or memory address because they are
    330255         * hardwired in the board, the probe should modify these fields.
    331          * Futhermore, the probe routine should also fill in de_initf and
    332          * de_stopf fields with the appropriate function pointers and set
    333          * de_prog_IO iff programmed I/O is to be used.
    334256         */
    335257        port_t de_base_port;
    336         phys_bytes de_linmem;
    337         char *de_locmem;
    338258        int de_irq;
    339         int de_int_pending;
    340 //      irq_hook_t de_hook;
    341         dp_initf_t de_initf;
    342         dp_stopf_t de_stopf;
    343         int de_prog_IO;
    344         char de_name[sizeof("dp8390#n")];
    345 
    346         /* The initf function fills the following fields. Only cards that do
    347          * programmed I/O fill in the de_pata_port field.
    348          * In addition, the init routine has to fill in the sendq data
    349          * structures.
    350          */
     259       
    351260        ether_addr_t de_address;
    352261        port_t de_dp8390_port;
    … …  
    357266        int de_startpage;
    358267        int de_stoppage;
    359 
    360         /* should be here - read even for ne2k isa init... */
    361         char de_pci;                    /* TRUE iff PCI device */
    362 
    363 #if ENABLE_PCI
    364         /* PCI config */
    365 //      char de_pci;                    /* TRUE iff PCI device */
    366 //      u8_t de_pcibus;
    367 //      u8_t de_pcidev;
    368 //      u8_t de_pcifunc;       
     268       
     269        /* Do it yourself send queue */
     270        struct sendq {
     271                int sq_filled;    /* this buffer contains a packet */
     272                int sq_size;      /* with this size */
     273                int sq_sendpage;  /* starting page of the buffer */
     274        } de_sendq[SENDQ_NR];
     275       
     276        int de_sendq_nr;
     277        int de_sendq_head;  /* Enqueue at the head */
     278        int de_sendq_tail;  /* Dequeue at the tail */
     279       
     280        /* Fields for internal use by the dp8390 driver. */
     281        eth_stat_t de_stat;
     282       
     283        /* Driver flags */
     284        bool up;
     285        bool enabled;
     286        bool stopped;
     287        bool sending;
     288        bool send_avail;
     289} dpeth_t;
     290
    369291#endif
    370292
    371         /* Do it yourself send queue */
    372         struct sendq
    373         {
    374                 int sq_filled;          /* this buffer contains a packet */
    375                 int sq_size;            /* with this size */
    376                 int sq_sendpage;        /* starting page of the buffer */
    377         } de_sendq[SENDQ_NR];
    378         int de_sendq_nr;
    379         int de_sendq_head;              /* Enqueue at the head */
    380         int de_sendq_tail;              /* Dequeue at the tail */
    381 
    382         /* Fields for internal use by the dp8390 driver. */
    383         int de_flags;
    384         int de_mode;
    385         eth_stat_t de_stat;
    386         iovec_dat_t de_read_iovec;
    387 //      iovec_dat_s_t de_read_iovec_s;
    388 //      int de_safecopy_read;
    389         iovec_dat_t de_write_iovec;
    390 //      iovec_dat_s_t de_write_iovec_s;
    391         iovec_dat_t de_tmp_iovec;
    392 //      iovec_dat_s_t de_tmp_iovec_s;
    393         vir_bytes de_read_s;
    394 //      int de_client;
    395 //      message de_sendmsg;
    396         dp_user2nicf_t de_user2nicf;
    397 //      dp_user2nicf_s_t de_user2nicf_s;
    398         dp_nic2userf_t de_nic2userf;
    399 //      dp_nic2userf_s_t de_nic2userf_s;
    400         dp_getblock_t de_getblockf;
    401 } dpeth_t;
    402 
    403 #define DEI_DEFAULT     0x8000
    404 
    405 #define DEF_EMPTY       0x000
    406 #define DEF_PACK_SEND   0x001
    407 #define DEF_PACK_RECV   0x002
    408 #define DEF_SEND_AVAIL  0x004
    409 #define DEF_READING     0x010
    410 #define DEF_PROMISC     0x040
    411 #define DEF_MULTI       0x080
    412 #define DEF_BROAD       0x100
    413 #define DEF_ENABLED     0x200
    414 #define DEF_STOPPED     0x400
    415 
    416 #define DEM_DISABLED    0x0
    417 #define DEM_SINK        0x1
    418 #define DEM_ENABLED     0x2
    419 
    420 //#if !__minix_vmd
    421 #define debug           1       /* Standard Minix lacks debug variable */
    422 //#endif
    423 
    424 /*
    425  * $PchId: dp8390.h,v 1.10 2005/02/10 17:26:06 philip Exp $
    426  */
    427 
    428 #endif
    429 
    430293/** @}
    431294 */
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