Changeset 9c2fb97 in mainline
- Timestamp:
- 2007-11-16T16:18:29Z (17 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 1b03ed3
- Parents:
- 296426ad
- Files:
-
- 3 edited
-
kernel/arch/mips32/include/stack.h (modified) (1 diff)
-
kernel/arch/mips32/src/start.S (modified) (7 diffs)
-
uspace/lib/libc/arch/mips32/src/syscall.c (modified) (3 diffs)
Legend:
- Unmodified
- Added
- Removed
-
kernel/arch/mips32/include/stack.h
r296426ad r9c2fb97 39 39 #define STACK_ALIGNMENT 8 40 40 41 #define STACK_ARG0 0 42 #define STACK_ARG1 4 43 #define STACK_ARG2 8 44 #define STACK_ARG3 12 45 #define STACK_ARG4 16 46 #define STACK_ARG5 20 47 #define STACK_ARG6 24 48 41 49 #endif 42 50 -
kernel/arch/mips32/src/start.S
r296426ad r9c2fb97 31 31 #include <arch/asm/boot.h> 32 32 #include <arch/context_offset.h> 33 #include <arch/stack.h> 33 34 34 35 .text … … 52 53 # SP is NOT saved as part of these registers 53 54 .macro REGISTERS_STORE_AND_EXC_RESET r 54 sw $at, EOFFSET_AT(\r)55 sw $v0, EOFFSET_V0(\r)56 sw $v1, EOFFSET_V1(\r)57 sw $a0, EOFFSET_A0(\r)58 sw $a1, EOFFSET_A1(\r)59 sw $a2, EOFFSET_A2(\r)60 sw $a3, EOFFSET_A3(\r)61 sw $t0, EOFFSET_T0(\r)62 sw $t1, EOFFSET_T1(\r)63 sw $t2, EOFFSET_T2(\r)64 sw $t3, EOFFSET_T3(\r)65 sw $t4, EOFFSET_T4(\r)66 sw $t5, EOFFSET_T5(\r)67 sw $t6, EOFFSET_T6(\r)68 sw $t7, EOFFSET_T7(\r)69 sw $t8, EOFFSET_T8(\r)70 sw $t9, EOFFSET_T9(\r)55 sw $at, EOFFSET_AT(\r) 56 sw $v0, EOFFSET_V0(\r) 57 sw $v1, EOFFSET_V1(\r) 58 sw $a0, EOFFSET_A0(\r) 59 sw $a1, EOFFSET_A1(\r) 60 sw $a2, EOFFSET_A2(\r) 61 sw $a3, EOFFSET_A3(\r) 62 sw $t0, EOFFSET_T0(\r) 63 sw $t1, EOFFSET_T1(\r) 64 sw $t2, EOFFSET_T2(\r) 65 sw $t3, EOFFSET_T3(\r) 66 sw $t4, EOFFSET_T4(\r) 67 sw $t5, EOFFSET_T5(\r) 68 sw $t6, EOFFSET_T6(\r) 69 sw $t7, EOFFSET_T7(\r) 70 sw $t8, EOFFSET_T8(\r) 71 sw $t9, EOFFSET_T9(\r) 71 72 72 73 mflo $at … … 76 77 77 78 #ifdef CONFIG_DEBUG_ALLREGS 78 sw $s0, EOFFSET_S0(\r)79 sw $s1, EOFFSET_S1(\r)80 sw $s2, EOFFSET_S2(\r)81 sw $s3, EOFFSET_S3(\r)82 sw $s4, EOFFSET_S4(\r)83 sw $s5, EOFFSET_S5(\r)84 sw $s6, EOFFSET_S6(\r)85 sw $s7, EOFFSET_S7(\r)86 sw $s8, EOFFSET_S8(\r)79 sw $s0, EOFFSET_S0(\r) 80 sw $s1, EOFFSET_S1(\r) 81 sw $s2, EOFFSET_S2(\r) 82 sw $s3, EOFFSET_S3(\r) 83 sw $s4, EOFFSET_S4(\r) 84 sw $s5, EOFFSET_S5(\r) 85 sw $s6, EOFFSET_S6(\r) 86 sw $s7, EOFFSET_S7(\r) 87 sw $s8, EOFFSET_S8(\r) 87 88 #endif 88 89 89 sw $gp, EOFFSET_GP(\r)90 sw $ra, EOFFSET_RA(\r)91 sw $k1, EOFFSET_K1(\r)90 sw $gp, EOFFSET_GP(\r) 91 sw $ra, EOFFSET_RA(\r) 92 sw $k1, EOFFSET_K1(\r) 92 93 93 94 mfc0 $t0, $status 94 95 mfc0 $t1, $epc 95 96 96 and $t2, $t0, REG_SAVE_MASK 97 and $t2, $t0, REG_SAVE_MASK # Save only KSU,EXL,ERL,IE 97 98 li $t3, ~(0x1f) 98 and $t0, $t0, $t3 99 and $t0, $t0, $t3 # Clear KSU,EXL,ERL,IE 99 100 100 101 sw $t2,EOFFSET_STATUS(\r) … … 109 110 lw $t1,EOFFSET_STATUS(\r) 110 111 111 li $t2, ~REG_SAVE_MASK 112 li $t2, ~REG_SAVE_MASK # Mask UM,EXL,ERL,IE 112 113 and $t0, $t0, $t2 113 114 114 or $t0, $t0, $t1 # Copy UM,EXL,ERL,IE from saved status115 or $t0, $t0, $t1 # Copy UM,EXL, ERL, IE from saved status 115 116 mtc0 $t0, $status 116 117 117 lw $v0, EOFFSET_V0(\r)118 lw $v1, EOFFSET_V1(\r)119 lw $a0, EOFFSET_A0(\r)120 lw $a1, EOFFSET_A1(\r)121 lw $a2, EOFFSET_A2(\r)122 lw $a3, EOFFSET_A3(\r)123 lw $t0, EOFFSET_T0(\r)124 lw $t1, EOFFSET_T1(\r)125 lw $t2, EOFFSET_T2(\r)126 lw $t3, EOFFSET_T3(\r)127 lw $t4, EOFFSET_T4(\r)128 lw $t5, EOFFSET_T5(\r)129 lw $t6, EOFFSET_T6(\r)130 lw $t7, EOFFSET_T7(\r)131 lw $t8, EOFFSET_T8(\r)132 lw $t9, EOFFSET_T9(\r)118 lw $v0, EOFFSET_V0(\r) 119 lw $v1, EOFFSET_V1(\r) 120 lw $a0, EOFFSET_A0(\r) 121 lw $a1, EOFFSET_A1(\r) 122 lw $a2, EOFFSET_A2(\r) 123 lw $a3, EOFFSET_A3(\r) 124 lw $t0, EOFFSET_T0(\r) 125 lw $t1, EOFFSET_T1(\r) 126 lw $t2, EOFFSET_T2(\r) 127 lw $t3, EOFFSET_T3(\r) 128 lw $t4, EOFFSET_T4(\r) 129 lw $t5, EOFFSET_T5(\r) 130 lw $t6, EOFFSET_T6(\r) 131 lw $t7, EOFFSET_T7(\r) 132 lw $t8, EOFFSET_T8(\r) 133 lw $t9, EOFFSET_T9(\r) 133 134 134 135 #ifdef CONFIG_DEBUG_ALLREGS 135 lw $s0, EOFFSET_S0(\r)136 lw $s1, EOFFSET_S1(\r)137 lw $s2, EOFFSET_S2(\r)138 lw $s3, EOFFSET_S3(\r)139 lw $s4, EOFFSET_S4(\r)140 lw $s5, EOFFSET_S5(\r)141 lw $s6, EOFFSET_S6(\r)142 lw $s7, EOFFSET_S7(\r)143 lw $s8, EOFFSET_S8(\r)136 lw $s0, EOFFSET_S0(\r) 137 lw $s1, EOFFSET_S1(\r) 138 lw $s2, EOFFSET_S2(\r) 139 lw $s3, EOFFSET_S3(\r) 140 lw $s4, EOFFSET_S4(\r) 141 lw $s5, EOFFSET_S5(\r) 142 lw $s6, EOFFSET_S6(\r) 143 lw $s7, EOFFSET_S7(\r) 144 lw $s8, EOFFSET_S8(\r) 144 145 #endif 145 lw $gp, EOFFSET_GP(\r)146 lw $ra, EOFFSET_RA(\r)147 lw $k1, EOFFSET_K1(\r)148 149 lw $at, EOFFSET_LO(\r)146 lw $gp, EOFFSET_GP(\r) 147 lw $ra, EOFFSET_RA(\r) 148 lw $k1, EOFFSET_K1(\r) 149 150 lw $at, EOFFSET_LO(\r) 150 151 mtlo $at 151 lw $at, EOFFSET_HI(\r)152 lw $at, EOFFSET_HI(\r) 152 153 mthi $at 153 154 154 lw $at, EOFFSET_EPC(\r)155 lw $at, EOFFSET_EPC(\r) 155 156 mtc0 $at, $epc 156 157 157 lw $at, EOFFSET_AT(\r)158 lw $sp, EOFFSET_SP(\r)158 lw $at, EOFFSET_AT(\r) 159 lw $sp, EOFFSET_SP(\r) 159 160 .endm 160 161 … … 229 230 j exception_handler 230 231 nop 231 232 233 232 234 233 exception_handler: 235 234 KERNEL_STACK_TO_K0 236 235 sub $k0, REGISTER_SPACE 237 sw $sp, EOFFSET_SP($k0)236 sw $sp, EOFFSET_SP($k0) 238 237 move $sp, $k0 239 238 240 239 mfc0 $k0, $cause 241 240 242 sra $k0, $k0, 0x2 243 andi $k0, $k0, 0x1f 244 sub $k0, 8 # 8=SYSCALL241 sra $k0, $k0, 0x2 # cp0_exc_cause() part 1 242 andi $k0, $k0, 0x1f # cp0_exc_cause() part 2 243 sub $k0, 8 # 8 = SYSCALL 245 244 246 245 beqz $k0, syscall_shortcut 247 add $k0, 8 246 add $k0, 8 # Revert $k0 back to correct exc number 248 247 249 248 REGISTERS_STORE_AND_EXC_RESET $sp 250 249 251 250 move $a1, $sp 252 jal exc_dispatch 251 jal exc_dispatch # exc_dispatch(excno, register_space) 253 252 move $a0, $k0 254 253 … … 257 256 eret 258 257 259 # it seems that mips reserves some space on stack for varfuncs??? 260 #define SS_ARG4 16 261 #define SS_SP EOFFSET_SP 262 #define SS_STATUS EOFFSET_STATUS 263 #define SS_EPC EOFFSET_EPC 264 #define SS_K1 EOFFSET_K1 258 ## Syscall entry 259 # 260 # Registers: 261 # 262 # @param v0 Syscall number. 263 # @param a0 1st argument. 264 # @param a1 2nd argument. 265 # @param a2 3rd argument. 266 # @param a3 4th argument. 267 # @param t0 5th argument. 268 # @param t1 6th argument. 269 # 270 # @return The return value will be stored in v0. 271 # 272 #define SS_SP EOFFSET_SP 273 #define SS_STATUS EOFFSET_STATUS 274 #define SS_EPC EOFFSET_EPC 275 #define SS_K1 EOFFSET_K1 265 276 syscall_shortcut: 266 277 # We have a lot of space on the stack, with free use 267 mfc0 $t1, $epc 268 mfc0 $t0, $status 269 sw $t1,SS_EPC($sp) # Save EPC 270 sw $k1,SS_K1($sp) # Save k1, which is not saved during context switch 271 272 and $t2, $t0, REG_SAVE_MASK # Save only KSU,EXL,ERL,IE 273 li $t3, ~(0x1f) 274 and $t0, $t0, $t3 # Clear KSU,EXL,ERL 275 ori $t0, $t0, 0x1 # Set IE 276 277 sw $t2,SS_STATUS($sp) 278 mtc0 $t0, $status 279 280 # CALL Syscall handler 278 mfc0 $t3, $epc 279 mfc0 $t2, $status 280 sw $t3, SS_EPC($sp) # Save EPC 281 sw $k1, SS_K1($sp) # Save k1 not saved on context switch 282 283 and $t4, $t2, REG_SAVE_MASK # Save only KSU, EXL, ERL, IE 284 li $t5, ~(0x1f) 285 and $t2, $t2, $t5 # Clear KSU, EXL, ERL 286 ori $t2, $t2, 0x1 # Set IE 287 288 sw $t4, SS_STATUS($sp) 289 mtc0 $t2, $status 290 291 # 292 # Call the higher level system call handler 293 # We are going to reuse part of the unused exception stack frame 294 # 295 sw $t0, STACK_ARG4($sp) # save the 5th argument on the stack 296 sw $t1, STACK_ARG5($sp) # save the 6th argument on the stack 281 297 jal syscall_handler 282 sw $v0, S S_ARG4($sp) # save v0 - arg4 tostack298 sw $v0, STACK_ARG6($sp) # save the syscall number on the stack 283 299 284 300 # restore status 285 mfc0 $t 0, $status286 lw $t 1,SS_STATUS($sp)287 288 # Change back to EXL =1(from last exception), otherwise289 # an interrupt could rewrite the CP0 -EPC290 li $t 2, ~REG_SAVE_MASK # Mask UM,EXL,ERL,IE291 and $t 0, $t0, $t2292 or $t 0, $t0, $t1 # Copy UM,EXL,ERL,IE from saved status293 mtc0 $t 0, $status301 mfc0 $t2, $status 302 lw $t3, SS_STATUS($sp) 303 304 # Change back to EXL = 1 (from last exception), otherwise 305 # an interrupt could rewrite the CP0 - EPC 306 li $t4, ~REG_SAVE_MASK # Mask UM, EXL, ERL, IE 307 and $t2, $t2, $t4 308 or $t2, $t2, $t3 # Copy saved UM, EXL, ERL, IE 309 mtc0 $t2, $status 294 310 295 # restore epc +4296 lw $t 0,SS_EPC($sp)297 lw $k1, SS_K1($sp)298 addi $t 0, $t0, 4299 mtc0 $t 0, $epc300 301 lw $sp, SS_SP($sp)# restore sp311 # restore epc + 4 312 lw $t2, SS_EPC($sp) 313 lw $k1, SS_K1($sp) 314 addi $t2, $t2, 4 315 mtc0 $t2, $epc 316 317 lw $sp, SS_SP($sp) # restore sp 302 318 303 319 eret … … 334 350 add $sp, $a0, 0 335 351 add $v0, $a1, 0 336 add $t9, $a2, 0 337 eret 352 add $t9, $a2, 0 # Set up correct entry into PIC code 353 eret -
uspace/lib/libc/arch/mips32/src/syscall.c
r296426ad r9c2fb97 36 36 #include <libc.h> 37 37 38 sysarg_t __syscall(const sysarg_t p1, const sysarg_t p2, 39 const sysarg_t p3, const sysarg_t p4, 40 const syscall_t id) 38 sysarg_t __syscall(const sysarg_t p1, const sysarg_t p2, const sysarg_t p3, 39 const sysarg_t p4, const sysarg_t p5, const sysarg_t p6, const syscall_t id) 41 40 { 42 41 register sysarg_t __mips_reg_a0 asm("$4") = p1; … … 44 43 register sysarg_t __mips_reg_a2 asm("$6") = p3; 45 44 register sysarg_t __mips_reg_a3 asm("$7") = p4; 45 register sysarg_t __mips_reg_t0 asm("$8") = p5; 46 register sysarg_t __mips_reg_t1 asm("$9") = p6; 46 47 register sysarg_t __mips_reg_v0 asm("$2") = id; 47 48 … … 53 54 "r" (__mips_reg_a2), 54 55 "r" (__mips_reg_a3), 56 "r" (__mips_reg_t0), 57 "r" (__mips_reg_t1), 55 58 "r" (__mips_reg_v0) 56 59 : "%ra" /* We are a function call, although C does not
Note:
See TracChangeset
for help on using the changeset viewer.
