Changeset a1a03f9 in mainline


Ignore:
Timestamp:
2005-07-14T22:10:05Z (20 years ago)
Author:
Jakub Jermar <jakub@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
26649537
Parents:
ff9f858
Message:

Begin MIPS implementation of 4-level page table interface.

Add email address to each item in doc/AUTHORS.

Correct type names in comments in mm/vm.c.
Introduce ptl0 pointer in vm_t.

Files:
9 edited

Legend:

Unmodified
Added
Removed

  • arch/ia64/include/mm/page.h

    rff9f858 ra1a03f9  
    3030#define __ia64_PAGE_H__
    3131
     32#include <arch/types.h>
    3233#include <arch/mm/frame.h>
    3334

  • arch/mips/include/mm/frame.h

    rff9f858 ra1a03f9  
    3030#define __mips_FRAME_H__
    3131
    32 #define FRAME_SIZE              4096
     32#define FRAME_SIZE              16384
    3333
    3434extern void frame_arch_init(void);

  • arch/mips/include/mm/page.h

    rff9f858 ra1a03f9  
    3030#define __mips_PAGE_H__
    3131
     32#include <arch/mm/tlb.h>
     33#include <mm/page.h>
    3234#include <arch/mm/frame.h>
    3335#include <arch/types.h>
     36#include <arch.h>
    3437
    3538#define PAGE_SIZE       FRAME_SIZE
    … …  
    3841#define PA2KA(x)        ((x) + 0x80000000)
    3942
    40 #define page_arch_init()        ;
    41 
    4243/*
    4344 * Implementation of generic 4-level page table interface.
    44  * TODO: this is a fake implementation provided to satisfy the compiler
     45 * NOTE: this implementation is under construction
     46 *
     47 * Page table layout:
     48 * - 32-bit virtual addresses
     49 * - Offset is 14 bits => pages are 16K long
     50 * - PTE's use the same format as CP0 EntryLo[01] registers => PTE is therefore 4 bytes long
     51 * - PTL0 has 64 entries (6 bits)
     52 * - PTL1 is not used
     53 * - PTL2 is not used
     54 * - PTL3 has 4096 entries (12 bits)
    4555 */
    46 #define PTL0_INDEX_ARCH(vaddr)  0
     56 
     57#define PTL0_INDEX_ARCH(vaddr)  ((vaddr)>>26)
    4758#define PTL1_INDEX_ARCH(vaddr)  0
    4859#define PTL2_INDEX_ARCH(vaddr)  0
    49 #define PTL3_INDEX_ARCH(vaddr)  0
     60#define PTL3_INDEX_ARCH(vaddr)  (((vaddr)>>14)&0xfff)
    5061
    51 #define GET_PTL0_ADDRESS_ARCH()                 ((pte_t *) 0)
    52 #define GET_PTL1_ADDRESS_ARCH(ptl0, i)          ((pte_t *) 0)
    53 #define GET_PTL2_ADDRESS_ARCH(ptl1, i)          ((pte_t *) 0)
    54 #define GET_PTL3_ADDRESS_ARCH(ptl2, i)          ((pte_t *) 0)
    55 #define GET_FRAME_ADDRESS_ARCH(ptl3, i)         ((pte_t *) 0)
     62#define GET_PTL0_ADDRESS_ARCH()                 (PTL0)
     63#define SET_PTL0_ADDRESS_ARCH(ptl0)             (PTL0 = (pte_t *)(ptl0))
    5664
    57 #define SET_PTL0_ADDRESS_ARCH(ptl0)
    58 #define SET_PTL1_ADDRESS_ARCH(ptl0, i, a)
     65#define GET_PTL1_ADDRESS_ARCH(ptl0, i)          (((pte_t *)(ptl0))[(i)].pfn<<14)
     66#define GET_PTL2_ADDRESS_ARCH(ptl1, i)          (ptl1)
     67#define GET_PTL3_ADDRESS_ARCH(ptl2, i)          (ptl2)
     68#define GET_FRAME_ADDRESS_ARCH(ptl3, i)         (((pte_t *)(ptl3))[(i)].pfn<<14)
     69
     70#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a)       (((pte_t *)(ptl0))[(i)].pfn = (a)>>14)
    5971#define SET_PTL2_ADDRESS_ARCH(ptl1, i, a)
    6072#define SET_PTL3_ADDRESS_ARCH(ptl2, i, a)
    61 #define SET_FRAME_ADDRESS_ARCH(ptl3, i, a)
     73#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a)      (((pte_t *)(ptl3))[(i)].pfn = (a)>>14)
    6274
    63 #define GET_PTL1_FLAGS_ARCH(ptl0, i)            0
    64 #define GET_PTL2_FLAGS_ARCH(ptl1, i)            0
    65 #define GET_PTL3_FLAGS_ARCH(ptl2, i)            0
    66 #define GET_FRAME_FLAGS_ARCH(ptl3, i)           0
     75#define GET_PTL1_FLAGS_ARCH(ptl0, i)            get_pt_flags((pte_t *)(ptl0), (index_t)(i))
     76#define GET_PTL2_FLAGS_ARCH(ptl1, i)            PAGE_PRESENT
     77#define GET_PTL3_FLAGS_ARCH(ptl2, i)            PAGE_PRESENT
     78#define GET_FRAME_FLAGS_ARCH(ptl3, i)           get_pt_flags((pte_t *)(ptl3), (index_t)(i))
    6779
    68 #define SET_PTL1_FLAGS_ARCH(ptl0, i, x)
     80#define SET_PTL1_FLAGS_ARCH(ptl0, i, x)         set_pt_flags((pte_t *)(ptl0), (index_t)(i), (x))
    6981#define SET_PTL2_FLAGS_ARCH(ptl1, i, x)
    7082#define SET_PTL3_FLAGS_ARCH(ptl2, i, x)
    71 #define SET_FRAME_FLAGS_ARCH(ptl3, i, x)
     83#define SET_FRAME_FLAGS_ARCH(ptl3, i, x)        set_pt_flags((pte_t *)(ptl3), (index_t)(i), (x))
    7284
    73 typedef __u32 pte_t;
     85static inline int get_pt_flags(pte_t *pt, index_t i)
     86{
     87        pte_t *p = &pt[i];
     88       
     89        return (
     90                ((p->c>PAGE_UNCACHED)<<PAGE_CACHEABLE_SHIFT) |
     91                ((!p->v)<<PAGE_PRESENT_SHIFT) |
     92                (1<<PAGE_USER_SHIFT) |
     93                (1<<PAGE_READ_SHIFT) |
     94                ((p->d)<<PAGE_WRITE_SHIFT) |
     95                (1<<PAGE_EXEC_SHIFT)
     96        );
     97               
     98}
     99
     100static inline void set_pt_flags(pte_t *pt, index_t i, int flags)
     101{
     102        pte_t *p = &pt[i];
     103       
     104        p->c = (flags & PAGE_CACHEABLE) ? PAGE_CACHEABLE_EXC_WRITE : PAGE_UNCACHED;
     105        p->v = !(flags & PAGE_NOT_PRESENT);
     106        p->d = flags & PAGE_WRITE;
     107}
     108
     109extern void page_arch_init(void);
     110
     111extern pte_t *PTL0;
    74112
    75113#endif

  • arch/mips/include/mm/tlb.h

    rff9f858 ra1a03f9  
    3030#define __mips_TLB_H__
    3131
     32#define PAGE_UNCACHED                   2
     33#define PAGE_CACHEABLE_EXC_WRITE        5
     34
    3235struct entry_lo {
    33         unsigned g : 1;
    34         unsigned v : 1;
    35         unsigned d : 1;
    36         unsigned c : 3;
    37         unsigned pfn : 24;
     36        unsigned g : 1;         /* global bit */
     37        unsigned v : 1;         /* valid bit */
     38        unsigned d : 1;         /* dirty/write-protect bit */
     39        unsigned c : 3;         /* cache coherency attribute */
     40        unsigned pfn : 24;      /* frame number */
    3841        unsigned : 2;
    3942} __attribute__ ((packed));
    … …  
    5962} __attribute__ ((packed));
    6063
     64typedef struct entry_lo pte_t;
     65
    6166extern void tlb_refill(void);
    6267extern void tlb_invalid(void);

  • arch/mips/src/mm/page.c

    rff9f858 ra1a03f9  
    2828
    2929#include <arch/types.h>
     30#include <arch/mm/page.h>
     31#include <arch/mm/frame.h>
     32#include <mm/frame.h>
    3033#include <mm/page.h>
     34
     35pte_t *PTL0 = NULL;
     36
     37void page_arch_init(void)
     38{
     39        __address ptl0;
     40       
     41        ptl0 = frame_alloc(FRAME_KA | FRAME_PANIC);
     42        memsetb(ptl0, FRAME_SIZE, 0);
     43       
     44        SET_PTL0_ADDRESS(KA2PA(ptl0));
     45}

  • doc/AUTHORS

    rff9f858 ra1a03f9  
    1 Jakub Jermar
    2 Jakub Vana
    3 Martin Decky
    4 Josef Cejka
    5 Sergey Bondari
    6 Ondrej Palkovsky
     1Jakub Jermar <jermar@itbs.cz>
     2Jakub Vana <jakub.vana@gmail.com>
     3Martin Decky <martin@decky.cz>
     4Josef Cejka <malyzelenyhnus@seznam.cz>
     5Sergey Bondari <bondari@itbs.cz>
     6Ondrej Palkovsky <ondrap@penguin.cz>

  • include/mm/page.h

    rff9f858 ra1a03f9  
    7777 * each descending by one level.
    7878 */
    79 #define GET_PTL0_ADDRESS()              GET_PTL0_ADDRESS_ARCH()
    8079#define GET_PTL1_ADDRESS(ptl0, i)       GET_PTL1_ADDRESS_ARCH(ptl0, i)
    8180#define GET_PTL2_ADDRESS(ptl1, i)       GET_PTL2_ADDRESS_ARCH(ptl1, i)
    … …  
    8786 * tree of page tables on respective level.
    8887 */
    89 #define SET_PTL0_ADDRESS(ptl0)          SET_PTL0_ADDRESS_ARCH(ptl0)
    9088#define SET_PTL1_ADDRESS(ptl0, i, a)    SET_PTL1_ADDRESS_ARCH(ptl0, i, a)
    9189#define SET_PTL2_ADDRESS(ptl1, i, a)    SET_PTL2_ADDRESS_ARCH(ptl1, i, a)

  • include/mm/vm.h

    rff9f858 ra1a03f9  
    3030#define __VM_H__
    3131
     32#include <arch/mm/page.h>
    3233#include <arch/mm/vm.h>
    3334#include <arch/types.h>
    … …  
    5253
    5354/*
    54  * Each vm_area structure describes one continuous area of virtual memory.
     55 * Each vm_area_t structure describes one continuous area of virtual memory.
    5556 * In the future, it should not be difficult to support shared areas of vm.
    5657 */
    … …  
    6566
    6667/*
    67  * vm_mapping_t contains the list of vm_areas of userspace accessible
     68 * vm_t contains the list of vm_areas of userspace accessible
    6869 * pages for one or more tasks. Ranges of kernel memory pages are not
    6970 * supposed to figure in the list as they are shared by all tasks and
    … …  
    7374        spinlock_t lock;
    7475        link_t vm_area_head;
     76        int j;
     77        pte_t *ptl0;
    7578};
    7679

  • src/mm/vm.c

    rff9f858 ra1a03f9  
    4949                spinlock_initialize(&m->lock);
    5050                list_initialize(&m->vm_area_head);
     51                m->ptl0 = NULL;
    5152        }
    5253       
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