Changeset a1a03f9 in mainline for arch/mips/include/mm/tlb.h

Timestamp:

2005-07-14T22:10:05Z (20 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

26649537

Parents:

ff9f858

Message:

Begin MIPS implementation of 4-level page table interface.

Add email address to each item in doc/AUTHORS.

Correct type names in comments in mm/vm.c.
Introduce ptl0 pointer in vm_t.

File:

• arch/mips/include/mm/tlb.h (modified) (2 diffs)

arch/mips/include/mm/tlb.h

@@ -30 +30 @@
 #define __mips_TLB_H__
 
+#define PAGE_UNCACHED                   2
+#define PAGE_CACHEABLE_EXC_WRITE        5
+
 struct entry_lo {
-        unsigned g : 1;
-        unsigned v : 1;
-        unsigned d : 1;
-        unsigned c : 3;
-        unsigned pfn : 24;
+        unsigned g : 1;         /* global bit */
+        unsigned v : 1;         /* valid bit */
+        unsigned d : 1;         /* dirty/write-protect bit */
+        unsigned c : 3;         /* cache coherency attribute */
+        unsigned pfn : 24;      /* frame number */
         unsigned : 2;
 } __attribute__ ((packed));
@@ -59 +62 @@
 } __attribute__ ((packed));
 
+typedef struct entry_lo pte_t;
+
 extern void tlb_refill(void);
 extern void tlb_invalid(void);