Changeset ad7a6c9 in mainline for kernel/arch/mips32/include/cp0.h

Timestamp:

2011-03-30T13:10:24Z (14 years ago)

Author:

Vojtech Horky <vojtechhorky@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

4ae90f9

Parents:

6e50466 (diff), d6b81941 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.

Message:

Merge mainline changes

File:

• kernel/arch/mips32/include/cp0.h (modified) (2 diffs)

kernel/arch/mips32/include/cp0.h

@@ -70 +70 @@
   { \
       uint32_t retval; \
-      asm("mfc0 %0, $" #reg : "=r"(retval)); \
+      asm volatile ("mfc0 %0, $" #reg : "=r"(retval)); \
       return retval; \
   }
@@ -76 +76 @@
 #define GEN_WRITE_CP0(nm,reg) static inline void cp0_ ##nm##_write(uint32_t val) \
  { \
-    asm("mtc0 %0, $" #reg : : "r"(val) ); \
+    asm volatile ("mtc0 %0, $" #reg : : "r"(val) ); \
  }