Changeset add04f7 in mainline for kernel/arch/ia32/include/asm.h
- Timestamp:
- 2009-03-03T15:20:49Z (16 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- f24d300
- Parents:
- deca67b
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
kernel/arch/ia32/include/asm.h
rdeca67b radd04f7 28 28 */ 29 29 30 /** @addtogroup ia32 30 /** @addtogroup ia32 31 31 * @{ 32 32 */ … … 57 57 * 58 58 * Halt the current CPU until interrupt event. 59 * 59 60 */ 60 61 static inline void cpu_halt(void) … … 69 70 70 71 #define GEN_READ_REG(reg) static inline unative_t read_ ##reg (void) \ 71 { \ 72 unative_t res; \ 73 asm volatile ("movl %%" #reg ", %0" : "=r" (res) ); \ 74 return res; \ 75 } 72 { \ 73 unative_t res; \ 74 asm volatile ( \ 75 "movl %%" #reg ", %[res]" \ 76 : [res] "=r" (res) \ 77 ); \ 78 return res; \ 79 } 76 80 77 81 #define GEN_WRITE_REG(reg) static inline void write_ ##reg (unative_t regn) \ 78 { \ 79 asm volatile ("movl %0, %%" #reg : : "r" (regn)); \ 80 } 82 { \ 83 asm volatile ( \ 84 "movl %[regn], %%" #reg \ 85 :: [regn] "r" (regn) \ 86 ); \ 87 } 81 88 82 89 GEN_READ_REG(cr0) … … 105 112 * @param port Port to write to 106 113 * @param val Value to write 114 * 107 115 */ 108 116 static inline void pio_write_8(ioport8_t *port, uint8_t val) 109 117 { 110 asm volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port)); 118 asm volatile ( 119 "outb %b[val], %w[port]\n" 120 :: [val] "a" (val), [port] "d" (port) 121 ); 111 122 } 112 123 … … 117 128 * @param port Port to write to 118 129 * @param val Value to write 130 * 119 131 */ 120 132 static inline void pio_write_16(ioport16_t *port, uint16_t val) 121 133 { 122 asm volatile ("outw %w0, %w1\n" : : "a" (val), "d" (port)); 134 asm volatile ( 135 "outw %w[val], %w[port]\n" 136 :: [val] "a" (val), [port] "d" (port) 137 ); 123 138 } 124 139 … … 129 144 * @param port Port to write to 130 145 * @param val Value to write 146 * 131 147 */ 132 148 static inline void pio_write_32(ioport32_t *port, uint32_t val) 133 149 { 134 asm volatile ("outl %0, %w1\n" : : "a" (val), "d" (port)); 150 asm volatile ( 151 "outl %[val], %w[port]\n" 152 :: [val] "a" (val), [port] "d" (port) 153 ); 135 154 } 136 155 … … 141 160 * @param port Port to read from 142 161 * @return Value read 162 * 143 163 */ 144 164 static inline uint8_t pio_read_8(ioport8_t *port) … … 146 166 uint8_t val; 147 167 148 asm volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port)); 168 asm volatile ( 169 "inb %w[port], %b[val]\n" 170 : [val] "=a" (val) 171 : [port] "d" (port) 172 ); 173 149 174 return val; 150 175 } … … 156 181 * @param port Port to read from 157 182 * @return Value read 183 * 158 184 */ 159 185 static inline uint16_t pio_read_16(ioport16_t *port) … … 161 187 uint16_t val; 162 188 163 asm volatile ("inw %w1, %w0 \n" : "=a" (val) : "d" (port)); 189 asm volatile ( 190 "inw %w[port], %w[val]\n" 191 : [val] "=a" (val) 192 : [port] "d" (port) 193 ); 194 164 195 return val; 165 196 } … … 171 202 * @param port Port to read from 172 203 * @return Value read 204 * 173 205 */ 174 206 static inline uint32_t pio_read_32(ioport32_t *port) … … 176 208 uint32_t val; 177 209 178 asm volatile ("inl %w1, %0 \n" : "=a" (val) : "d" (port)); 210 asm volatile ( 211 "inl %w[port], %[val]\n" 212 : [val] "=a" (val) 213 : [port] "d" (port) 214 ); 215 179 216 return val; 180 217 } … … 186 223 * 187 224 * @return Old interrupt priority level. 225 * 188 226 */ 189 227 static inline ipl_t interrupts_enable(void) 190 228 { 191 229 ipl_t v; 192 asm volatile ( 193 "pushf\n\t" 194 "popl %0\n\t" 230 231 asm volatile ( 232 "pushf\n" 233 "popl %[v]\n" 195 234 "sti\n" 196 : "=r" (v) 197 ); 235 : [v] "=r" (v) 236 ); 237 198 238 return v; 199 239 } … … 205 245 * 206 246 * @return Old interrupt priority level. 247 * 207 248 */ 208 249 static inline ipl_t interrupts_disable(void) 209 250 { 210 251 ipl_t v; 211 asm volatile ( 212 "pushf\n\t" 213 "popl %0\n\t" 252 253 asm volatile ( 254 "pushf\n" 255 "popl %[v]\n" 214 256 "cli\n" 215 : "=r" (v) 216 ); 257 : [v] "=r" (v) 258 ); 259 217 260 return v; 218 261 } … … 223 266 * 224 267 * @param ipl Saved interrupt priority level. 268 * 225 269 */ 226 270 static inline void interrupts_restore(ipl_t ipl) 227 271 { 228 272 asm volatile ( 229 "pushl % 0\n\t"273 "pushl %[ipl]\n" 230 274 "popf\n" 231 : :"r" (ipl)275 :: [ipl] "r" (ipl) 232 276 ); 233 277 } … … 236 280 * 237 281 * @return EFLAFS. 282 * 238 283 */ 239 284 static inline ipl_t interrupts_read(void) 240 285 { 241 286 ipl_t v; 242 asm volatile ( 243 "pushf\n\t" 244 "popl %0\n" 245 : "=r" (v) 246 ); 287 288 asm volatile ( 289 "pushf\n" 290 "popl %[v]\n" 291 : [v] "=r" (v) 292 ); 293 247 294 return v; 248 295 } … … 251 298 static inline void write_msr(uint32_t msr, uint64_t value) 252 299 { 253 asm volatile ("wrmsr" : : "c" (msr), "a" ((uint32_t)(value)), 254 "d" ((uint32_t)(value >> 32))); 300 asm volatile ( 301 "wrmsr" 302 :: "c" (msr), "a" ((uint32_t) (value)), 303 "d" ((uint32_t) (value >> 32)) 304 ); 255 305 } 256 306 … … 258 308 { 259 309 uint32_t ax, dx; 260 261 asm volatile ("rdmsr" : "=a"(ax), "=d"(dx) : "c" (msr)); 262 return ((uint64_t)dx << 32) | ax; 310 311 asm volatile ( 312 "rdmsr" 313 : "=a" (ax), "=d" (dx) 314 : "c" (msr) 315 ); 316 317 return ((uint64_t) dx << 32) | ax; 263 318 } 264 319 … … 269 324 * The stack is assumed to be STACK_SIZE bytes long. 270 325 * The stack must start on page boundary. 326 * 271 327 */ 272 328 static inline uintptr_t get_stack_base(void) … … 275 331 276 332 asm volatile ( 277 "andl %%esp, % 0\n"278 : "=r" (v)333 "andl %%esp, %[v]\n" 334 : [v] "=r" (v) 279 335 : "0" (~(STACK_SIZE - 1)) 280 336 ); … … 287 343 { 288 344 uintptr_t *ip; 289 290 asm volatile ( 291 "mov %%eip, %0" 292 : "=r" (ip) 293 ); 345 346 asm volatile ( 347 "mov %%eip, %[ip]" 348 : [ip] "=r" (ip) 349 ); 350 294 351 return ip; 295 352 } … … 298 355 * 299 356 * @param addr Address on a page whose TLB entry is to be invalidated. 357 * 300 358 */ 301 359 static inline void invlpg(uintptr_t addr) 302 360 { 303 asm volatile ("invlpg %0\n" :: "m" (*(unative_t *)addr)); 361 asm volatile ( 362 "invlpg %[addr]\n" 363 :: [addr] "m" (*(unative_t *) addr) 364 ); 304 365 } 305 366 … … 307 368 * 308 369 * @param gdtr_reg Address of memory from where to load GDTR. 370 * 309 371 */ 310 372 static inline void gdtr_load(ptr_16_32_t *gdtr_reg) 311 373 { 312 asm volatile ("lgdtl %0\n" : : "m" (*gdtr_reg)); 374 asm volatile ( 375 "lgdtl %[gdtr_reg]\n" 376 :: [gdtr_reg] "m" (*gdtr_reg) 377 ); 313 378 } 314 379 … … 316 381 * 317 382 * @param gdtr_reg Address of memory to where to load GDTR. 383 * 318 384 */ 319 385 static inline void gdtr_store(ptr_16_32_t *gdtr_reg) 320 386 { 321 asm volatile ("sgdtl %0\n" : : "m" (*gdtr_reg)); 387 asm volatile ( 388 "sgdtl %[gdtr_reg]\n" 389 :: [gdtr_reg] "m" (*gdtr_reg) 390 ); 322 391 } 323 392 … … 325 394 * 326 395 * @param idtr_reg Address of memory from where to load IDTR. 396 * 327 397 */ 328 398 static inline void idtr_load(ptr_16_32_t *idtr_reg) 329 399 { 330 asm volatile ("lidtl %0\n" : : "m" (*idtr_reg)); 400 asm volatile ( 401 "lidtl %[idtr_reg]\n" 402 :: [idtr_reg] "m" (*idtr_reg) 403 ); 331 404 } 332 405 … … 334 407 * 335 408 * @param sel Selector specifying descriptor of TSS segment. 409 * 336 410 */ 337 411 static inline void tr_load(uint16_t sel) 338 412 { 339 asm volatile ("ltr %0" : : "r" (sel)); 413 asm volatile ( 414 "ltr %[sel]" 415 :: [sel] "r" (sel) 416 ); 340 417 } 341 418
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