Changeset b994a60 in mainline


Ignore:
Timestamp:
2006-03-09T12:44:27Z (19 years ago)
Author:
Jakub Jermar <jakub@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
901122b
Parents:
cd373bb
Message:

ia64 work.
Changes to make userspace work (kernel part).
Use ski.conf from contrib directory to run Ski.

There is actually no appropriate syscall handler yet.

Files:
12 edited

Legend:

Unmodified
Added
Removed

  • arch/ia64/Makefile.inc

    rcd373bb rb994a60  
    3939#
    4040
     41INIT_ADDRESS = 0xe000000000400000
     42INIT_SIZE = 0x100000
     43
    4144CFLAGS += -mconstant-gp -fno-unwind-tables
    4245LFLAGS += -EL
    4346AFLAGS += -mconstant-gp
     47
     48DEFS += -DINIT_ADDRESS=$(INIT_ADDRESS) -DINIT_SIZE=$(INIT_SIZE)
    4449
    4550## Compile with page hash table support.

  • arch/ia64/include/asm.h

    rcd373bb rb994a60  
    4949}
    5050
     51/** Return Processor State Register.
     52 *
     53 * @return PSR.
     54 */
     55static inline __u64 psr_read(void)
     56{
     57        __u64 v;
     58       
     59        __asm__ volatile ("mov %0 = psr\n" : "=r" (v));
     60       
     61        return v;
     62}
     63
    5164/** Read IVA (Interruption Vector Address).
    5265 *
    … …  
    233246static inline ipl_t interrupts_read(void)
    234247{
    235         __u64 v;
    236        
    237         __asm__ volatile ("mov %0 = psr\n" : "=r" (v));
    238        
    239         return (ipl_t) v;
     248        return (ipl_t) psr_read();
    240249}
    241250
    … …  
    250259extern void asm_delay_loop(__u32 t);
    251260
     261extern void switch_to_userspace(__address entry, __address sp, __address bsp, __u64 ipsr, __u64 rsc);
     262
    252263#endif

  • arch/ia64/include/context.h

    rcd373bb rb994a60  
    3131
    3232#include <arch/types.h>
     33#include <arch/register.h>
    3334#include <typedefs.h>
    3435#include <align.h>
    … …  
    4243 */
    4344#define SP_DELTA        (0+ALIGN_UP(STACK_ITEM_SIZE, STACK_ALIGNMENT))
    44 
    45 #define PFM_MASK        (~0x3fffffffff)
    4645
    4746#ifdef context_set

  • arch/ia64/include/mm/as.h

    rcd373bb rb994a60  
    3232#include <arch/types.h>
    3333
    34 #define KERNEL_ADDRESS_SPACE_START_ARCH         (__address) 0x8000000000000000
    35 #define KERNEL_ADDRESS_SPACE_END_ARCH           (__address) 0xffffffffffffffff
    36 #define USER_ADDRESS_SPACE_START_ARCH           (__address) 0x0000000000000000
    37 #define USER_ADDRESS_SPACE_END_ARCH             (__address) 0x7fffffffffffffff
     34#define KERNEL_ADDRESS_SPACE_START_ARCH         (__address) 0xe000000000000000ULL
     35#define KERNEL_ADDRESS_SPACE_END_ARCH           (__address) 0xffffffffffffffffULL
     36#define USER_ADDRESS_SPACE_START_ARCH           (__address) 0x0000000000000000ULL
     37#define USER_ADDRESS_SPACE_END_ARCH             (__address) 0xdfffffffffffffffULL
    3838
    39 #define UTEXT_ADDRESS_ARCH      0x0000000000001000
    40 #define USTACK_ADDRESS_ARCH     (0x7fffffffffffffff-(PAGE_SIZE-1))
    41 #define UDATA_ADDRESS_ARCH      0x0000000001001000
     39#define UTEXT_ADDRESS_ARCH      0x0000000000010000ULL
     40#define USTACK_ADDRESS_ARCH     0x0000000ff0000000ULL
     41#define UDATA_ADDRESS_ARCH      0x0000000001010000ULL
    4242
    4343extern void as_arch_init(void);

  • arch/ia64/include/register.h

    rcd373bb rb994a60  
    3030#define __ia64_REGISTER_H__
    3131
    32 #ifndef __ASM__
    33 #include <arch/types.h>
    34 #endif
    35 
    3632#define CR_IVR_MASK     0xf
    3733#define PSR_IC_MASK     0x2000
    … …  
    4541#define PSR_CPL_SHIFT           32
    4642#define PSR_CPL_MASK_SHIFTED    3
     43
     44#define PFM_MASK        (~0x3fffffffff)
     45
     46#define RSC_MODE_MASK   3
     47#define RSC_PL_MASK     12
    4748
    4849/** Application registers. */
    … …  
    121122
    122123#ifndef __ASM__
     124
     125#include <arch/types.h>
     126
     127/** Processor Status Register. */
     128union psr {
     129        __u64 value;
     130        struct {
     131                unsigned : 1;
     132                unsigned be : 1;        /**< Big-Endian data accesses. */
     133                unsigned up : 1;        /**< User Performance monitor enable. */
     134                unsigned ac : 1;        /**< Alignment Check. */
     135                unsigned mfl : 1;       /**< Lower floating-point register written. */
     136                unsigned mfh : 1;       /**< Upper floating-point register written. */
     137                unsigned : 7;
     138                unsigned ic : 1;        /**< Interruption Collection. */
     139                unsigned i : 1;         /**< Interrupt Bit. */
     140                unsigned pk : 1;        /**< Protection Key enable. */
     141                unsigned : 1;
     142                unsigned dt : 1;        /**< Data address Translation. */
     143                unsigned dfl : 1;       /**< Disabled Floating-point Low register set. */
     144                unsigned dfh : 1;       /**< Disabled Floating-point High register set. */
     145                unsigned sp : 1;        /**< Secure Performance monitors. */
     146                unsigned pp : 1;        /**< Privileged Performance monitor enable. */
     147                unsigned di : 1;        /**< Disable Instruction set transition. */
     148                unsigned si : 1;        /**< Secure Interval timer. */
     149                unsigned db : 1;        /**< Debug Breakpoint fault. */
     150                unsigned lp : 1;        /**< Lower Privilege transfer trap. */
     151                unsigned tb : 1;        /**< Taken Branch trap. */
     152                unsigned rt : 1;        /**< Register Stack Translation. */
     153                unsigned : 4;
     154                unsigned cpl : 2;       /**< Current Privilege Level. */
     155                unsigned is : 1;        /**< Instruction Set. */
     156                unsigned mc : 1;        /**< Machine Check abort mask. */
     157                unsigned it : 1;        /**< Instruction address Translation. */
     158                unsigned id : 1;        /**< Instruction Debug fault disable. */
     159                unsigned da : 1;        /**< Disable Data Access and Dirty-bit faults. */
     160                unsigned dd : 1;        /**< Data Debug fault disable. */
     161                unsigned ss : 1;        /**< Single Step enable. */
     162                unsigned ri : 2;        /**< Restart Instruction. */
     163                unsigned ed : 1;        /**< Exception Deferral. */
     164                unsigned bn : 1;        /**< Register Bank. */
     165                unsigned ia : 1;        /**< Disable Instruction Access-bit faults. */
     166        } __attribute__ ((packed));
     167};
     168typedef union psr psr_t;
     169
     170/** Register Stack Configuration Register */
     171union rsc {
     172        __u64 value;
     173        struct {
     174                unsigned mode : 2;
     175                unsigned pl : 2;        /**< Privilege Level. */
     176                unsigned be : 1;        /**< Big-endian. */
     177                unsigned : 11;
     178                unsigned loadrs : 14;
     179        } __attribute__ ((packed));
     180};
     181typedef union rsc rsc_t;
     182
    123183/** External Interrupt Vector Register */
    124184union cr_ivr {

  • arch/ia64/src/asm.S

    rcd373bb rb994a60  
    2727#
    2828
     29#include <arch/register.h>
     30
    2931.text
    3032
    … …  
    4749        }
    4850        br halt
     51
     52/** Switch to userspace - low level code.
     53 *
     54 * @param in0 Userspace entry point address.
     55 * @param in1 Userspace stack pointer address.
     56 * @param in2 Userspace register stack pointer address.
     57 * @param in3 Value to be stored in IPSR.
     58 * @param in4 Value to be stored in RSC.
     59 */
     60.global switch_to_userspace
     61switch_to_userspace:
     62        alloc loc0 = ar.pfs, 5, 3, 0, 0
     63        rsm (PSR_IC_MASK | PSR_I_MASK)          /* disable interruption collection  and interrupts */
     64        srlz.d ;;
     65        srlz.i ;;
     66       
     67        mov cr.ipsr = in3
     68        mov cr.iip = in0
     69        mov r12 = in1
     70
     71        xor r1 = r1, r1
     72       
     73        mov loc1 = cr.ifs
     74        movl loc2 = PFM_MASK ;;
     75        and loc1 = loc2, loc1 ;;
     76        mov cr.ifs = loc1 ;;                    /* prevent decrementing BSP by rfi */
     77
     78        invala
     79       
     80        mov loc1 = ar.rsc ;;
     81        and loc1 = ~3, loc1 ;;                 
     82        mov ar.rsc = loc1 ;;                    /* put RSE into enforced lazy mode */
     83
     84        flushrs ;;
     85       
     86        mov ar.bspstore = in2 ;;
     87        mov ar.rsc = in4 ;;
     88       
     89        rfi ;;

  • arch/ia64/src/dummy.s

    rcd373bb rb994a60  
    3131.global calibrate_delay_loop
    3232.global asm_delay_loop
    33 .global userspace
    3433.global cpu_sleep
    3534.global dummy
    … …  
    3837.global fpu_init
    3938
    40 userspace:
    4139calibrate_delay_loop:
    4240asm_delay_loop:

  • arch/ia64/src/ia64.c

    rcd373bb rb994a60  
    3232#include <arch/interrupt.h>
    3333#include <arch/barrier.h>
     34#include <arch/asm.h>
     35#include <arch/register.h>
    3436#include <arch/types.h>
    35 
     37#include <arch/context.h>
     38#include <arch/mm/page.h>
     39#include <mm/as.h>
     40#include <config.h>
     41#include <userspace.h>
    3642#include <console/console.h>
    3743
    … …  
    4450        ski_init_console();
    4551        it_init();
     52        config.init_addr = INIT_ADDRESS;
     53        config.init_size = INIT_SIZE;
    4654}
    4755
    … …  
    5462}
    5563
    56 
    5764void arch_post_smp_init(void)
    5865{
    5966}
     67
     68/** Enter userspace and never return. */
     69void userspace(void)
     70{
     71        psr_t psr;
     72        rsc_t rsc;
     73
     74        psr.value = psr_read();
     75        psr.cpl = PL_USER;
     76        psr.i = true;                           /* start with interrupts enabled */
     77        psr.ic = true;
     78        psr.ri = 0;                             /* start with instruction #0 */
     79
     80        __asm__ volatile ("mov %0 = ar.rsc\n" : "=r" (rsc.value));
     81        rsc.loadrs = 0;
     82        rsc.be = false;
     83        rsc.pl = PL_USER;
     84        rsc.mode = 3;                           /* eager mode */
     85
     86        switch_to_userspace(UTEXT_ADDRESS, USTACK_ADDRESS+PAGE_SIZE-1, USTACK_ADDRESS, psr.value, rsc.value);
     87
     88        while (1) {
     89                ;
     90        }
     91}

  • arch/ia64/src/ivt.S

    rcd373bb rb994a60  
    137137        st8 [r31] = r26, -8             /* save ar.ifs */
    138138       
    139         and r30 = ~3, r24 ;;
    140         mov ar.rsc = r30 ;;             /* place RSE in enforced lazy mode */
     139        and r24 = ~(RSC_PL_MASK), r24 ;;
     140        and r30 = ~(RSC_MODE_MASK), r24 ;;
     141        mov ar.rsc = r30 ;;             /* update RSE state */
    141142       
    142143        mov r27 = ar.rnat
    … …  
    163164        st8 [r31] = r29, -8             /* save ar.bsp */
    164165       
    165         mov ar.rsc = r24                /* restore RSE's setting */
     166        mov ar.rsc = r24                /* restore RSE's setting + kernel privileges */
    166167       
    167168    /* steps 6 - 15 are done by heavyweight_handler_inner() */
    … …  
    301302
    302303    /* 10. call handler */
     304        movl r1 = _hardcoded_load_address
     305   
    303306        mov b1 = loc2
    304307        br.call.sptk.many b0 = b1

  • arch/ia64/src/mm/tlb.c

    rcd373bb rb994a60  
    6464 * @param entry The rest of TLB entry as required by TLB insertion format.
    6565 */
    66 void dtc_mapping_insert(__address va, asid_t asid, tlb_entry_t entry) {
     66void dtc_mapping_insert(__address va, asid_t asid, tlb_entry_t entry)
     67{
    6768        tc_mapping_insert(va, asid, entry, true);
    6869}
    … …  
    7475 * @param entry The rest of TLB entry as required by TLB insertion format.
    7576 */
    76 void itc_mapping_insert(__address va, asid_t asid, tlb_entry_t entry) {
     77void itc_mapping_insert(__address va, asid_t asid, tlb_entry_t entry)
     78{
    7779        tc_mapping_insert(va, asid, entry, false);
    7880}
    … …  
    336338                }
    337339        }
    338        
     340
    339341        t = page_mapping_find(AS, va);
    340342        if (t) {

  • arch/ia64/src/start.S

    rcd373bb rb994a60  
    125125
    126126        # initialize gp (Global Pointer) register
    127         movl r1 = _hardcoded_load_address       ;;
     127        movl r1 = _hardcoded_load_address
    128128
    129129        /*
    … …  
    132132        movl r14 = _hardcoded_ktext_size
    133133        movl r15 = _hardcoded_kdata_size
    134         movl r16 = _hardcoded_load_address
     134        movl r16 = _hardcoded_load_address ;;
    135135        addl r17 = @gprel(hardcoded_ktext_size), gp
    136136        addl r18 = @gprel(hardcoded_kdata_size), gp

  • contrib/conf/ski.conf

    rcd373bb rb994a60  
    1 load SPARTAN/kernel.bin
    2 load SPARTAN/load.bin
     1load HelenOS/boot/kernel.bin
     2romload HelenOS/boot/init 0x400000
Note: See TracChangeset for help on using the changeset viewer.