Changeset c520034 in mainline for kernel/arch/arm32/include/mm/page.h

Timestamp:

2011-12-31T18:19:35Z (13 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

295f658, 77c2b02, 96cd5b4

Parents:

852052d (diff), 22f0561 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.

Message:

Support for kernel non-identity mappings, phase I.

• identity/non-identity kernel memory split on all architectures
• low/high physical memory split on all architectures
• frame allocator understands low/high memory
• high physical memory currently unused (Phase II)
• more compact frame_t
• zone conf frames, pte_t, kernel stacks allocated from low memory
• lockless TLB-miss handlers everywhere (newly sparc64, ia64)
• preallocate PTL1 page tables for non-identity and prevent their deallocation
• hw_map() unification
• new resource allocator used for allocating kernel virtual addresses

Breakage:

• sparc64/sun4v creates too large kernel identity; not fixed because of lack of testing hw
• ppc32's tlb_refill() seems wrong as it creates too large kernel identity, but appears unused and the architecture works normally

Not implemented yet (phase II):

• allow high memory to be used for common kernel allocations

File:

• kernel/arch/arm32/include/mm/page.h (modified) (1 diff)

kernel/arch/arm32/include/mm/page.h

@@ -54 +54 @@
 
 /* Number of entries in each level. */
-#define PTL0_ENTRIES_ARCH       (2 << 12)       /* 4096 */
+#define PTL0_ENTRIES_ARCH       (1 << 12)       /* 4096 */
 #define PTL1_ENTRIES_ARCH       0
 #define PTL2_ENTRIES_ARCH       0
 /* coarse page tables used (256 * 4 = 1KB per page) */
-#define PTL3_ENTRIES_ARCH       (2 << 8)        /* 256 */
+#define PTL3_ENTRIES_ARCH       (1 << 8)        /* 256 */
 
 /* Page table sizes for each level. */