Changeset c90aed4 in mainline

Timestamp:

2013-05-23T17:25:28Z (12 years ago)

Author:

Martin Decky <martin@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

192565b, 94dfb92

Parents:

4a5a18be

Message:

explicitly enable PCI bus mastering for each PCI bus function (this fixes #539)
a nicer way would be to enable the bus mastering only for devices/functions actually claimed by a driver, but the DDF needs some polishing in these areas

Location:

uspace/drv/bus/pci/pciintel

Files:

• pci.c (modified) (2 diffs)
• pci.h (modified) (1 diff)
• pci_regs.h (modified) (1 diff)

uspace/drv/bus/pci/pciintel/pci.c

@@ -327 +327 @@
 
         /* Vendor ID & Device ID, length(incl \0) 22 */
-        rc = snprintf(match_id_str, ID_MAX_STR_LEN, "pci/ven=%04x&dev=%04x",
-            fun->vendor_id, fun->device_id);
+        rc = snprintf(match_id_str, ID_MAX_STR_LEN, "pci/ven=%04"
+            PRIx16 "&dev=%04" PRIx16, fun->vendor_id, fun->device_id);
         if (rc < 0) {
                 ddf_msg(LVL_ERROR, "Failed creating match ID str: %s",
@@ -758 +758 @@
         fun->vendor_id = pci_conf_read_16(fun, PCI_VENDOR_ID);
         fun->device_id = pci_conf_read_16(fun, PCI_DEVICE_ID);
+        
+        /* Explicitly enable PCI bus mastering */
+        fun->command = pci_conf_read_16(fun, PCI_COMMAND) |
+            PCI_COMMAND_MASTER;
+        pci_conf_write_16(fun, PCI_COMMAND, fun->command);
+        
         fun->class_code = pci_conf_read_8(fun, PCI_BASE_CLASS);
         fun->subclass_code = pci_conf_read_8(fun, PCI_SUB_CLASS);

uspace/drv/bus/pci/pciintel/pci.h

@@ -59 +59 @@
         int dev;
         int fn;
-        int vendor_id;
-        int device_id;
+        uint16_t vendor_id;
+        uint16_t device_id;
+        uint16_t command;
         uint8_t class_code;
         uint8_t subclass_code;

uspace/drv/bus/pci/pciintel/pci_regs.h

@@ -95 +95 @@
 #define PCI_BRIDGE_CTL                  0x3E
 
+/* PCI command flags */
+#define PCI_COMMAND_IO            0x001
+#define PCI_COMMAND_MEMORY        0x002
+#define PCI_COMMAND_MASTER        0x004
+#define PCI_COMMAND_SPECIAL       0x008
+#define PCI_COMMAND_INVALIDATE    0x010
+#define PCI_COMMAND_VGA_PALETTE   0x020
+#define PCI_COMMAND_PARITY        0x040
+#define PCI_COMMAND_WAIT          0x080
+#define PCI_COMMAND_SERR          0x100
+#define PCI_COMMAND_FAST_BACK     0x200
+#define PCI_COMMAND_INTX_DISABLE  0x400
+
 #endif