Changeset cd1e6b62 in mainline for kernel/arch/mips32/include/cp0.h


Ignore:
Timestamp:
2011-03-28T15:45:46Z (14 years ago)
Author:
Jan Vesely <jano.vesely@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
e353e85
Parents:
d70765d (diff), 51e5608 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.
Message:

Development branch changes

File:
1 edited

Legend:

Unmodified
Added
Removed
  • kernel/arch/mips32/include/cp0.h

    rd70765d rcd1e6b62  
    7070  { \
    7171      uint32_t retval; \
    72       asm("mfc0 %0, $" #reg : "=r"(retval)); \
     72      asm volatile ("mfc0 %0, $" #reg : "=r"(retval)); \
    7373      return retval; \
    7474  }
     
    7676#define GEN_WRITE_CP0(nm,reg) static inline void cp0_ ##nm##_write(uint32_t val) \
    7777 { \
    78     asm("mtc0 %0, $" #reg : : "r"(val) ); \
     78    asm volatile ("mtc0 %0, $" #reg : : "r"(val) ); \
    7979 }
    8080
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