Changeset e5dc7b8 in mainline

Timestamp:

2006-06-11T16:38:24Z (19 years ago)

Author:

Ondrej Palkovsky <ondrap@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

0b917dd

Parents:

8060a24c

Message:

Fix either bad compiler or bad code. The net result is better
optimization in GCC

File:

• arch/ia32/include/atomic.h (modified) (2 diffs)

arch/ia32/include/atomic.h

@@ -53 +53 @@
 static inline long atomic_postinc(atomic_t *val) 
 {
-        long r;
+        long r = 1;
 
         __asm__ volatile (
-                "movl $1, %0\n"
-                "lock xaddl %0, %1\n"
-                : "=r" (r), "=m" (val->count)
+                "lock xaddl %1, %0\n"
+                : "=m" (val->count) : "r" (r)
         );
 
@@ -66 +65 @@
 static inline long atomic_postdec(atomic_t *val) 
 {
-        long r;
+        long r = -1;
         
         __asm__ volatile (
-                "movl $-1, %0\n"
-                "lock xaddl %0, %1\n"
-                : "=r" (r), "=m" (val->count)
+                "lock xaddl %1, %0\n"
+                : "=m" (val->count) : "r"(r)
         );