Changeset f701b236 in mainline for arch/ia32/include/smp/apic.h

Timestamp:

2005-11-24T00:46:43Z (19 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

9149135

Parents:

8418c7d

Message:

More SMP cleanup.
Suddenly, keyboard started to work on SMP under Simics.
Still not functional on Bochs (will consult Bochs people).
Doxygen style comments for apic.c.

File:

• arch/ia32/include/smp/apic.h (modified) (7 diffs)

arch/ia32/include/smp/apic.h

@@ -71 +71 @@
 #define POLARITY_HIGH   0x0
 #define POLARITY_LOW    0x1
+
+/** Divide Values. (Bit 2 is always 0) */
+#define DIVIDE_2        0x0
+#define DIVIDE_4        0x1
+#define DIVIDE_8        0x2
+#define DIVIDE_16       0x3
+#define DIVIDE_32       0x8
+#define DIVIDE_64       0x9
+#define DIVIDE_128      0xa
+#define DIVIDE_1        0xb
+
+/** Timer Modes. */
+#define TIMER_ONESHOT   0x0
+#define TIMER_PERIODIC  0x1
 
 #define SEND_PENDING    (1<<12)
@@ -106 +120 @@
 #define EOI             (0x0b0/sizeof(__u32))
 
-/* Error Status Register */
+/** Error Status Register. */
 #define ESR             (0x280/sizeof(__u32))
-#define ESRClear        ((0xffffff<<8)|(1<<4))
+union esr {
+        __u32 value;
+        __u8 err_bitmap;
+        struct {
+                unsigned send_checksum_error : 1;
+                unsigned receive_checksum_error : 1;
+                unsigned send_accept_error : 1;
+                unsigned receive_accept_error : 1;
+                unsigned : 1;
+                unsigned send_illegal_vector : 1;
+                unsigned received_illegal_vector : 1;
+                unsigned illegal_register_address : 1;
+                unsigned : 24;
+        } __attribute__ ((packed));
+};
+typedef union esr esr_t;
 
 /* Task Priority Register */
@@ -127 +156 @@
 typedef union svr svr_t;
 
-/* Time Divide Configuration Register */
+/** Time Divide Configuration Register. */
 #define TDCR            (0x3e0/sizeof(__u32))
-#define TDCRClear       (~0xb)
+union tdcr {
+        __u32 value;
+        struct {
+                unsigned div_value : 4;         /**< Divide Value, bit 2 is always 0. */
+                unsigned : 28;                  /**< Reserved. */
+        } __attribute__ ((packed));
+};
+typedef union tdcr tdcr_t;
 
 /* Initial Count Register for Timer */
@@ -136 +172 @@
 /* Current Count Register for Timer */
 #define CCRT            (0x390/sizeof(__u32))
-
-/** Timer Modes. */
-#define TIMER_ONESHOT   0x0
-#define TIMER_PERIODIC  0x1
 
 /** LVT Timer register. */
@@ -191 +223 @@
 typedef union lvt_error lvt_error_t;
 
-
-#define LVT_PCINT       (0x340/sizeof(__u32))
-
-/* Local APIC ID Register */
+/** Local APIC ID Register. */
 #define L_APIC_ID       (0x020/sizeof(__u32))
-#define L_APIC_IDClear  (~(0xf<<24))
-#define L_APIC_IDShift  24
-#define L_APIC_IDMask   0xf
+union lapic_id {
+        __u32 value;
+        struct {
+                unsigned : 24;          /**< Reserved. */
+                __u8 apic_id;           /**< Local APIC ID. */
+        } __attribute__ ((packed));
+};
+typedef union lapic_id lapic_id_t;
 
 /* Local APIC Version Register */
@@ -215 +249 @@
 #define IOAPICARB       0x02
 #define IOREDTBL        0x10
+
+/** I/O Register Select Register. */
+union io_regsel {
+        __u32 value;
+        struct {
+                __u8 reg_addr;          /**< APIC Register Address. */
+                unsigned : 24;          /**< Reserved. */
+        } __attribute__ ((packed));
+};
+typedef union io_regsel io_regsel_t;
 
 /** I/O Redirection Register. */
@@ -262 +306 @@
 extern __u32 io_apic_read(__u8 address);
 extern void io_apic_write(__u8 address , __u32 x);
-extern void io_apic_change_ioredtbl(int signal, int dest, __u8 v, int flags);
+extern void io_apic_change_ioredtbl(int pin, int dest, __u8 v, int flags);
 extern void io_apic_disable_irqs(__u16 irqmask);
 extern void io_apic_enable_irqs(__u16 irqmask);