Changeset f834cc32 in mainline

Timestamp:

2015-09-23T19:59:06Z (9 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

8ca6f08

Parents:

a1d636e

Message:

More generic detection of TLB type.

Location:

kernel/arch/arm32

Files:

• include/arch/cp15.h (modified) (2 diffs)
• src/mm/tlb.c (modified) (1 diff)

kernel/arch/arm32/include/arch/cp15.h

@@ -118 +118 @@
 };
 CONTROL_REG_GEN_READ(CTR, c0, 0, c0, 1);
+
+#if defined(PROCESSOR_ARCH_armv6) || defined(PROCESSOR_ARCH_armv7_a)
 CONTROL_REG_GEN_READ(TCMR, c0, 0, c0, 2);
+
+enum {
+        TLBTR_SEP_FLAG = 1,
+};
+
 CONTROL_REG_GEN_READ(TLBTR, c0, 0, c0, 3);
+#endif
+
+#if defined(PROCESSOR_ARCH_armv7_a)
 CONTROL_REG_GEN_READ(MPIDR, c0, 0, c0, 5);
 CONTROL_REG_GEN_READ(REVIDR, c0, 0, c0, 6);
+#endif
 
 enum {
@@ -442 +453 @@
 
 CONTROL_REG_GEN_WRITE(TLBIALL, c8, 0, c7, 0);
-#if !defined(PROCESSOR_arm920t)
 CONTROL_REG_GEN_WRITE(TLBIMVA, c8, 0, c7, 1);
-#endif
 #if defined(PROCESSOR_ARCH_armv6) || defined(PROCESSOR_ARCH_armv7_a)
 CONTROL_REG_GEN_WRITE(TLBIASID, c8, 0, c7, 2);

kernel/arch/arm32/src/mm/tlb.c

@@ -79 +79 @@
 static inline void invalidate_page(uintptr_t page)
 {
-#if defined(PROCESSOR_arm920t)
+#if defined(PROCESSOR_ARCH_armv6) || defined(PROCESSOR_ARCH_armv7_a)
+        if (TLBTR_read() & TLBTR_SEP_FLAG) {
+                ITLBIMVA_write(page);
+                DTLBIMVA_write(page);
+        } else {
+                TLBIMVA_write(page);
+        }
+#elif defined(PROCESSOR_arm920t)
         ITLBIMVA_write(page);
         DTLBIMVA_write(page);
+#elif defined(PROCESSOR_arm926ej_s)
+        TLBIMVA_write(page);
 #else
-        //TODO: What about TLBIMVAA?
-        TLBIMVA_write(page);
+#error Unknown TLB type
 #endif
+
         /*
          * "A TLB maintenance operation is only guaranteed to be complete after