Virtual address spaces per architecture
Below are the various situations as dictated by hardware of each supported architecture and as currently used by HelenOS. The address space split is described from the kernel's point of view.
amd64
48-bit virtual address width
| Starting address | Size | HW limitation
|
|---|
FFFF800000000000 | 128 TiB | none
|
0000800000000000 | 16776960 TiB | VA hole(1)
|
0000000000000000 | 128 TiB | none
|
- depends on implementation, but in practice current implementations use 48 bits
arm32
| Starting address | Size | HW limitation
|
|---|
80000000 | 2 GiB | high vectors at fixed VA(1)
|
00000000 | 2 GiB | low vectors at fixed VA(2)
|
-
0xFFFF0000 - 0xFFFF001C
-
0x00000000 - 0x0000001C
ia32
| Starting address | Size | HW limitation
|
|---|
80000000 | 2 GiB | none
|
00000000 | 2 GiB | none
|
ia64
Itanium
(3 + 51)-bit virtual address width
| Starting address | Size | HW limitation
|
|---|
FFFC000000000000 | 1 PiB | VRN 7, high
|
E004000000000000 | 2046 PiB | VA hole
|
E000000000000000 | 1 PiB | VRN 7, low
|
DFFC000000000000 | 1 PiB | VRN 6, high
|
C004000000000000 | 2046 PiB | VA hole
|
C000000000000000 | 1 PiB | VRN 6, low
|
BFFC000000000000 | 1 PiB | VRN 5, high
|
A004000000000000 | 2046 PiB | VA hole
|
A000000000000000 | 1 PiB | VRN 5, low
|
9FFC000000000000 | 1 PiB | VRN 4, high
|
8004000000000000 | 2046 PiB | VA hole
|
8000000000000000 | 1 PiB | VRN 4, low
|
7FFC000000000000 | 1 PiB | VRN 3, high
|
6004000000000000 | 2046 PiB | VA hole
|
6000000000000000 | 1 PiB | VRN 3, low
|
5FFC000000000000 | 1 PiB | VRN 2, high
|
4004000000000000 | 2046 PiB | VA hole
|
4000000000000000 | 1 PiB | VRN 2, low
|
3FFC000000000000 | 1 PiB | VRN 1, high
|
2004000000000000 | 2046 PiB | VA hole
|
2000000000000000 | 1 PiB | VRN 1, low
|
1FFC000000000000 | 1 PiB | VRN 0, high
|
0004000000000000 | 2046 PiB | VA hole
|
0000000000000000 | 1 PiB | VRN 0, low
|
Itanium 2
| Starting address | Size | HW limitation
|
|---|
E000000000000000 | 2 EiB | VRN 7
|
C000000000000000 | 2 EiB | VRN 6
|
A000000000000000 | 2 EiB | VRN 5
|
8000000000000000 | 2 EiB | VRN 4
|
6000000000000000 | 2 EiB | VRN 3
|
4000000000000000 | 2 EiB | VRN 2
|
2000000000000000 | 2 EiB | VRN 1
|
0000000000000000 | 2 EiB | VRN 0
|
mips32
| Starting address | Size | HW limitation
|
|---|
E0000000 | 512 MiB | kseg3, kernel
|
C0000000 | 512 MiB | ksseg, kernel
|
A0000000 | 512 MiB | kseg1, kernel uncached(1)
|
80000000 | 512 MiB | kseg0, kernel identity(2)
|
00000000 | 2 GiB | kuseg, uspace
|
- maps to physical 0, uncached, bypasses TLB
- maps to physical 0, cacheable, bypasses TLB
ppc32
| Starting address | Size | HW limitation
|
|---|
80000000 | 2 GiB | none
|
00000000 | 2 GiB | none
|
sparc64
UltraSPARC I, II, IIi
44-bit virtual address width
| Starting address | Size | HW limitation
|
|---|
FFFFF80000000000 | 8 TiB | kernel(1)
|
0000080000000000 | 16777200 TiB | VA hole(2)
|
0000000000000000 | 8 TiB | kernel(1)
|
UltraSPARC III, IIIi, IV and IV+
64-bit virtual address width
| Starting address | Size | HW limitation
|
|---|
0000000000000000 | 16 EiB | kernel(1)
|
UltraSPARC T1, T2
48-bit virtual address width
| Starting address | Size | HW limitation
|
|---|
FFFF800000000000 | 128 TiB | kernel(1)
|
0000800000000000 | 16776960 TiB | VA hole(3), (4)
|
0000000000000000 | 128 TiB | kernel(1)
|
- both kernel and uspace run in separated 64-bit address spaces
- no code within 4GiB reach of the VA hole on UltraSPARC I and II
- no code within 4GiB reach of the VA hole on T1
- no code within 8KiB below VA hole on T2
