Changeset 005b765 in mainline for kernel/arch/arm32/include/barrier.h

Timestamp:

2013-01-24T22:07:06Z (12 years ago)

Author:

Jan Vesely <jano.vesely@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

03362fbd, 3acd1bb, d59c046

Parents:

6218d4b (diff), 24bead17 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.

Message:

Merge arm improvements.

Speed up boot by enabling caches early (but disable before jumping to kernel).
Add cycle counters on armv7.
Move bbxm dispc driver to uspace.
Add arm PROCESSOR and PROCESSOR_ARCH defines.

File:

• kernel/arch/arm32/include/barrier.h (modified) (3 diffs)

kernel/arch/arm32/include/barrier.h

@@ -37 +37 @@
 #define KERN_arm32_BARRIER_H_
 
-/*
- * TODO: implement true ARM memory barriers for macros below.
- * ARMv6 introduced user access of the following commands:
- * • Prefetch flush
- * • Data synchronization barrier
- * • Data memory barrier
- * • Clean and prefetch range operations.
- * ARM Architecture Reference Manual version I ch. B.3.2.1 p. B3-4
- */
+#ifdef KERNEL
+#include <arch/cp15.h>
+#else
+#include <libarch/cp15.h>
+#endif
+
 #define CS_ENTER_BARRIER()  asm volatile ("" ::: "memory")
 #define CS_LEAVE_BARRIER()  asm volatile ("" ::: "memory")
@@ -60 +57 @@
 #define read_barrier()    asm volatile ("dsb" ::: "memory")
 #define write_barrier()   asm volatile ("dsb st" ::: "memory")
+#define inst_barrier()    asm volatile ("isb" ::: "memory")
+#elif defined PROCESSOR_ARCH_armv6 | defined KERNEL
+/*
+ * ARMv6 introduced user access of the following commands:
+ * - Prefetch flush
+ * - Data synchronization barrier
+ * - Data memory barrier
+ * - Clean and prefetch range operations.
+ * ARM Architecture Reference Manual version I ch. B.3.2.1 p. B3-4
+ */
+/* ARMv6- use system control coprocessor (CP15) for memory barrier instructions.
+ * Although at least mcr p15, 0, r0, c7, c10, 4 is mentioned in earlier archs,
+ * CP15 implementation is mandatory only for armv6+.
+ */
+#define memory_barrier()  CP15DMB_write(0)
+#define read_barrier()    CP15DSB_write(0)
+#define write_barrier()   read_barrier()
+#define inst_barrier()    CP15ISB_write(0)
 #else
+/* Older manuals mention syscalls as a way to implement cache coherency and
+ * barriers. See for example ARM Architecture Reference Manual Version D
+ * chapter 2.7.4 Prefetching and self-modifying code (p. A2-28)
+ */
+// TODO implement on per PROCESSOR basis or via syscalls
 #define memory_barrier()  asm volatile ("" ::: "memory")
 #define read_barrier()    asm volatile ("" ::: "memory")
 #define write_barrier()   asm volatile ("" ::: "memory")
+#define inst_barrier()    asm volatile ("" ::: "memory")
 #endif
+
 /*
  * There are multiple ways ICache can be implemented on ARM machines. Namely
@@ -80 +102 @@
  */
 
-#ifdef PROCESSOR_ARCH_armv7_a
-#define smc_coherence(a) asm volatile ( "isb" ::: "memory")
-#define smc_coherence_block(a, l) smc_coherence(a)
-#else
+#if defined PROCESSOR_ARCH_armv7_a | defined PROCESSOR_ARCH_armv6 | defined KERNEL
 /* Available on all supported arms,
  * invalidates entire ICache so the written value does not matter. */
-//TODO might be PL1 only on armv5 -
-#define smc_coherence(a) asm volatile ( "mcr p15, 0, r0, c7, c5, 0")
-#define smc_coherence_block(a, l) smc_coherence(a)
+//TODO might be PL1 only on armv5-
+#define smc_coherence(a) \
+do { \
+        DCCMVAU_write((uint32_t)(a));  /* Flush changed memory */\
+        write_barrier();               /* Wait for completion */\
+        ICIALLU_write(0);              /* Flush ICache */\
+        inst_barrier();                /* Wait for Inst refetch */\
+} while (0)
+/* @note: Cache type register is not available in uspace. We would need
+ * to export the cache line value, or use syscall for uspace smc_coherence */
+#define smc_coherence_block(a, l) \
+do { \
+        for (uintptr_t addr = (uintptr_t)a; addr < (uintptr_t)a + l; addr += 4)\
+                smc_coherence(addr); \
+} while (0)
+#else
+#define smc_coherence(a)
+#define smc_coherence_block(a, l)
 #endif