Changeset 029e3cc in mainline for boot/arch/arm32/src/mm.c

Timestamp:

2013-01-01T11:44:47Z (12 years ago)

Author:

Jan Vesely <jano.vesely@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

4a46ccc

Parents:

a4afc8d (diff), b5a3b50 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.

Message:

Mainline changes (boot caching for gta02)

File:

• boot/arch/arm32/src/mm.c (modified) (3 diffs)

boot/arch/arm32/src/mm.c

@@ -38 +38 @@
 #include <arch/mm.h>
 
+/** Check if caching can be enabled for a given memory section.
+ *
+ * Memory areas used for I/O are excluded from caching.
+ * At the moment caching is enabled only on GTA02.
+ *
+ * @param section       The section number.
+ *
+ * @return      1 if the given section can be mapped as cacheable, 0 otherwise.
+*/
+static inline int section_cacheable(pfn_t section)
+{
+#ifdef MACHINE_gta02
+        unsigned long address = section << PTE_SECTION_SHIFT;
+
+        if (address >= GTA02_IOMEM_START && address < GTA02_IOMEM_END)
+                return 0;
+        else
+                return 1;
+#else
+        return 0;
+#endif
+}
+
 /** Initialize "section" page table entry.
  *
@@ -55 +78 @@
         pte->descriptor_type = PTE_DESCRIPTOR_SECTION;
         pte->bufferable = 1;
-        pte->cacheable = 0;
+        pte->cacheable = section_cacheable(frame);
         pte->xn = 0;
         pte->domain = 0;
@@ -130 +153 @@
                 "ldr r1, =0x00000805\n"
 #else
+#ifdef MACHINE_gta02
+                /* Mask to enable paging (bit 0),
+                   D-cache (bit 2), I-cache (bit 12) */
+                "ldr r1, =0x00001005\n"
+#else
                 /* Mask to enable paging and branch prediction */
                 "ldr r1, =0x00000801\n"
+#endif
 #endif
                 "orr r0, r0, r1\n"