Changeset 0882a9a in mainline


Ignore:
Timestamp:
2006-02-10T16:11:14Z (19 years ago)
Author:
Jakub Jermar <jakub@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
ecbdc724
Parents:
d0a0f12
Message:

Make use of one unused bit in PTE formats of amd64, ia32 and mips32 to store 1 in valid mappings.
This helps to distinguish valid entries from not present entries with 0 content (i.e. not present
entries with PFN 0 and other bits cleared).

Files:
7 edited

Legend:

Unmodified
Added
Removed

  • arch/amd64/include/mm/page.h

    rd0a0f12 r0882a9a  
    7676#ifndef __ASM__
    7777
     78/** Page Table Entry. */
    7879struct page_specifier {
    7980        unsigned present : 1;
    … …  
    8687        unsigned unused: 1;
    8788        unsigned global : 1;
    88         unsigned avl : 3;
     89        unsigned soft_valid : 1;                /**< Valid content even if present bit is cleared. */
     90        unsigned avl : 2;
    8991        unsigned addr_12_31 : 30;
    9092        unsigned addr_32_51 : 21;
    … …  
    125127        p->no_execute = (flags & PAGE_EXEC) == 0;
    126128        p->global = (flags & PAGE_GLOBAL) != 0;
     129       
     130        /*
     131         * Ensure that there is at least one bit set even if the present bit is cleared.
     132         */
     133        p->soft_valid = 1;
    127134}
    128135

  • arch/ia32/include/mm/page.h

    rd0a0f12 r0882a9a  
    7878#include <typedefs.h>
    7979
     80/** Page Table Entry. */
    8081struct page_specifier {
    8182        unsigned present : 1;
    … …  
    8889        unsigned pat : 1;
    8990        unsigned global : 1;
    90         unsigned avl : 3;
     91        unsigned soft_valid : 1;        /**< Valid content even if the present bit is not set. */
     92        unsigned avl : 2;
    9193        unsigned frame_address : 20;
    9294} __attribute__ ((packed));
    … …  
    116118        p->writeable = (flags & PAGE_WRITE) != 0;
    117119        p->global = (flags & PAGE_GLOBAL) != 0;
     120       
     121        /*
     122         * Ensure that there is at least one bit set even if the present bit is cleared.
     123         */
     124        p->soft_valid = true;
    118125}
    119126

  • arch/mips32/include/mm/page.h

    rd0a0f12 r0882a9a  
    4949 * - Offset is 14 bits => pages are 16K long
    5050 * - PTE's use similar format as CP0 EntryLo[01] registers => PTE is therefore 4 bytes long
     51 * - PTE's replace EntryLo v (valid) bit with p (present) bit
     52 * - PTE's use only one bit to distinguish between cacheable and uncacheable mappings
     53 * - PTE's define soft_valid field to ensure there is at least one 1 bit even if the p bit is cleared
    5154 * - PTE's make use of CP0 EntryLo's two-bit reserved field for bit W (writable) and bit A (accessed)
    5255 * - PTL0 has 64 entries (6 bits)
    … …  
    6366#define SET_PTL0_ADDRESS_ARCH(ptl0)
    6467
    65 #define GET_PTL1_ADDRESS_ARCH(ptl0, i)          (((pte_t *)(ptl0))[(i)].lo.pfn<<12)
     68#define GET_PTL1_ADDRESS_ARCH(ptl0, i)          (((pte_t *)(ptl0))[(i)].pfn<<12)
    6669#define GET_PTL2_ADDRESS_ARCH(ptl1, i)          (ptl1)
    6770#define GET_PTL3_ADDRESS_ARCH(ptl2, i)          (ptl2)
    68 #define GET_FRAME_ADDRESS_ARCH(ptl3, i)         (((pte_t *)(ptl3))[(i)].lo.pfn<<12)
     71#define GET_FRAME_ADDRESS_ARCH(ptl3, i)         (((pte_t *)(ptl3))[(i)].pfn<<12)
    6972
    70 #define SET_PTL1_ADDRESS_ARCH(ptl0, i, a)       (((pte_t *)(ptl0))[(i)].lo.pfn = (a)>>12)
     73#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a)       (((pte_t *)(ptl0))[(i)].pfn = (a)>>12)
    7174#define SET_PTL2_ADDRESS_ARCH(ptl1, i, a)
    7275#define SET_PTL3_ADDRESS_ARCH(ptl2, i, a)
    73 #define SET_FRAME_ADDRESS_ARCH(ptl3, i, a)      (((pte_t *)(ptl3))[(i)].lo.pfn = (a)>>12)
     76#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a)      (((pte_t *)(ptl3))[(i)].pfn = (a)>>12)
    7477
    7578#define GET_PTL1_FLAGS_ARCH(ptl0, i)            get_pt_flags((pte_t *)(ptl0), (index_t)(i))
    … …  
    9598       
    9699        return (
    97                 ((p->lo.c>PAGE_UNCACHED)<<PAGE_CACHEABLE_SHIFT) |
    98                 ((!p->lo.v)<<PAGE_PRESENT_SHIFT) |
     100                (p->cacheable<<PAGE_CACHEABLE_SHIFT) |
     101                ((!p->p)<<PAGE_PRESENT_SHIFT) |
    99102                (1<<PAGE_USER_SHIFT) |
    100103                (1<<PAGE_READ_SHIFT) |
    101104                ((p->w)<<PAGE_WRITE_SHIFT) |
    102105                (1<<PAGE_EXEC_SHIFT) |
    103                 p->lo.g<<PAGE_GLOBAL_SHIFT
     106                (p->g<<PAGE_GLOBAL_SHIFT)
    104107        );
    105108               
    … …  
    110113        pte_t *p = &pt[i];
    111114       
    112         p->lo.c = (flags & PAGE_CACHEABLE) != 0 ? PAGE_CACHEABLE_EXC_WRITE : PAGE_UNCACHED;
    113         p->lo.v = !(flags & PAGE_NOT_PRESENT);
    114         p->lo.g = (flags & PAGE_GLOBAL) != 0;
     115        p->cacheable = (flags & PAGE_CACHEABLE) != 0;
     116        p->p = !(flags & PAGE_NOT_PRESENT);
     117        p->g = (flags & PAGE_GLOBAL) != 0;
    115118        p->w = (flags & PAGE_WRITE) != 0;
     119       
     120        /*
     121         * Ensure that valid entries have at least one bit set.
     122         */
     123        p->soft_valid = 1;
    116124}
    117125

  • arch/mips32/include/mm/tlb.h

    rd0a0f12 r0882a9a  
    6464};
    6565
    66 union pte {
    67         entry_lo_t lo;
    68         struct {
    69                 unsigned : 30;
    70                 unsigned w : 1;         /* writable */
    71                 unsigned a : 1;         /* accessed */
    72         } __attribute__ ((packed));
     66/** Page Table Entry. */
     67struct pte {
     68        unsigned g : 1;                 /**< Global bit. */
     69        unsigned p : 1;                 /**< Present bit. */
     70        unsigned d : 1;                 /**< Dirty bit. */
     71        unsigned cacheable : 1;         /**< Cacheable bit. */
     72        unsigned : 1;                   /**< Unused. */
     73        unsigned soft_valid : 1;        /**< Valid content even if not present. */
     74        unsigned pfn : 24;              /**< Physical frame number. */
     75        unsigned w : 1;                 /**< Page writable bit. */
     76        unsigned a : 1;                 /**< Accessed bit. */
    7377};
    7478

  • arch/mips32/include/types.h

    rd0a0f12 r0882a9a  
    5050typedef __u32 __native;
    5151
    52 typedef union pte pte_t;
     52typedef struct pte pte_t;
    5353
    5454typedef __u32 pfn_t;

  • arch/mips32/src/mm/tlb.c

    rd0a0f12 r0882a9a  
    4646static pte_t *find_mapping_and_check(__address badvaddr);
    4747
    48 static void prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, int c, __address pfn);
     48static void prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, bool cacheable, __address pfn);
    4949static void prepare_entry_hi(entry_hi_t *hi, asid_t asid, __address addr);
    5050
    … …  
    105105
    106106        prepare_entry_hi(&hi, AS->asid, badvaddr);
    107         prepare_entry_lo(&lo, pte->lo.g, pte->lo.v, pte->lo.d, pte->lo.c, pte->lo.pfn);
     107        prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->cacheable, pte->pfn);
    108108
    109109        /*
    … …  
    179179        pte->a = 1;
    180180
    181         prepare_entry_lo(&lo, pte->lo.g, pte->lo.v, pte->lo.d, pte->lo.c, pte->lo.pfn);
     181        prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->cacheable, pte->pfn);
    182182
    183183        /*
    … …  
    253253         */
    254254        pte->a = 1;
    255         pte->lo.d = 1;
    256 
    257         prepare_entry_lo(&lo, pte->lo.g, pte->lo.v, pte->w, pte->lo.c, pte->lo.pfn);
     255        pte->d = 1;
     256
     257        prepare_entry_lo(&lo, pte->g, pte->p, pte->w, pte->cacheable, pte->pfn);
    258258
    259259        /*
    … …  
    338338         */     
    339339        pte = page_mapping_find(AS, badvaddr);
    340         if (pte && pte->lo.v) {
     340        if (pte && pte->p) {
    341341                /*
    342342                 * Mapping found in page tables.
    … …  
    355355                         */
    356356                        pte = page_mapping_find(AS, badvaddr);
    357                         ASSERT(pte && pte->lo.v);
     357                        ASSERT(pte && pte->p);
    358358                        return pte;
    359359                }
    … …  
    371371         * Handler cannot succeed if the mapping is marked as invalid.
    372372         */
    373         if (!pte->lo.v) {
     373        if (!pte->p) {
    374374                printf("Invalid mapping.\n");
    375375                return NULL;
    … …  
    379379}
    380380
    381 void prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, int c, __address pfn)
     381void prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, bool cacheable, __address pfn)
    382382{
    383383        lo->value = 0;
    … …  
    385385        lo->v = v;
    386386        lo->d = d;
    387         lo->c = c;
     387        lo->c = cacheable ? PAGE_CACHEABLE_EXC_WRITE : PAGE_UNCACHED;
    388388        lo->pfn = pfn;
    389389}

  • genarch/src/mm/asid_fifo.c

    rd0a0f12 r0882a9a  
    3535#define FIFO_STATIC_LIMIT       1024
    3636#define FIFO_STATIC             (ASIDS_ALLOCABLE<FIFO_STATIC_LIMIT)
     37
    3738/**
    3839 * FIFO queue containing unassigned ASIDs.
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