Changeset 0882a9a in mainline for arch/mips32/include/mm/page.h

Timestamp:

2006-02-10T16:11:14Z (19 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

ecbdc724

Parents:

d0a0f12

Message:

Make use of one unused bit in PTE formats of amd64, ia32 and mips32 to store 1 in valid mappings.
This helps to distinguish valid entries from not present entries with 0 content (i.e. not present
entries with PFN 0 and other bits cleared).

File:

• arch/mips32/include/mm/page.h (modified) (4 diffs)

arch/mips32/include/mm/page.h

@@ -49 +49 @@
  * - Offset is 14 bits => pages are 16K long
  * - PTE's use similar format as CP0 EntryLo[01] registers => PTE is therefore 4 bytes long
+ * - PTE's replace EntryLo v (valid) bit with p (present) bit
+ * - PTE's use only one bit to distinguish between cacheable and uncacheable mappings
+ * - PTE's define soft_valid field to ensure there is at least one 1 bit even if the p bit is cleared
  * - PTE's make use of CP0 EntryLo's two-bit reserved field for bit W (writable) and bit A (accessed)
  * - PTL0 has 64 entries (6 bits)
@@ -63 +66 @@
 #define SET_PTL0_ADDRESS_ARCH(ptl0)
 
-#define GET_PTL1_ADDRESS_ARCH(ptl0, i)          (((pte_t *)(ptl0))[(i)].lo.pfn<<12)
+#define GET_PTL1_ADDRESS_ARCH(ptl0, i)          (((pte_t *)(ptl0))[(i)].pfn<<12)
 #define GET_PTL2_ADDRESS_ARCH(ptl1, i)          (ptl1)
 #define GET_PTL3_ADDRESS_ARCH(ptl2, i)          (ptl2)
-#define GET_FRAME_ADDRESS_ARCH(ptl3, i)         (((pte_t *)(ptl3))[(i)].lo.pfn<<12)
+#define GET_FRAME_ADDRESS_ARCH(ptl3, i)         (((pte_t *)(ptl3))[(i)].pfn<<12)
 
-#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a)       (((pte_t *)(ptl0))[(i)].lo.pfn = (a)>>12)
+#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a)       (((pte_t *)(ptl0))[(i)].pfn = (a)>>12)
 #define SET_PTL2_ADDRESS_ARCH(ptl1, i, a)
 #define SET_PTL3_ADDRESS_ARCH(ptl2, i, a)
-#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a)      (((pte_t *)(ptl3))[(i)].lo.pfn = (a)>>12)
+#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a)      (((pte_t *)(ptl3))[(i)].pfn = (a)>>12)
 
 #define GET_PTL1_FLAGS_ARCH(ptl0, i)            get_pt_flags((pte_t *)(ptl0), (index_t)(i))
@@ -95 +98 @@
         
         return (
-                ((p->lo.c>PAGE_UNCACHED)<<PAGE_CACHEABLE_SHIFT) |
-                ((!p->lo.v)<<PAGE_PRESENT_SHIFT) |
+                (p->cacheable<<PAGE_CACHEABLE_SHIFT) |
+                ((!p->p)<<PAGE_PRESENT_SHIFT) |
                 (1<<PAGE_USER_SHIFT) |
                 (1<<PAGE_READ_SHIFT) |
                 ((p->w)<<PAGE_WRITE_SHIFT) |
                 (1<<PAGE_EXEC_SHIFT) |
-                p->lo.g<<PAGE_GLOBAL_SHIFT
+                (p->g<<PAGE_GLOBAL_SHIFT)
         );
                 
@@ -110 +113 @@
         pte_t *p = &pt[i];
         
-        p->lo.c = (flags & PAGE_CACHEABLE) != 0 ? PAGE_CACHEABLE_EXC_WRITE : PAGE_UNCACHED;
-        p->lo.v = !(flags & PAGE_NOT_PRESENT);
-        p->lo.g = (flags & PAGE_GLOBAL) != 0;
+        p->cacheable = (flags & PAGE_CACHEABLE) != 0;
+        p->p = !(flags & PAGE_NOT_PRESENT);
+        p->g = (flags & PAGE_GLOBAL) != 0;
         p->w = (flags & PAGE_WRITE) != 0;
+        
+        /*
+         * Ensure that valid entries have at least one bit set.
+         */
+        p->soft_valid = 1;
 }