Changeset 10b890b in mainline for kernel/arch/sparc64/src/mm/tlb.c


Ignore:
Timestamp:
2006-07-13T22:11:26Z (19 years ago)
Author:
Jakub Jermar <jakub@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
c6e314a
Parents:
a5f76758
Message:

Move functionality of tlb_arch_init() to take_over_tlb_and_tt().
Call take_over_tlb_and_tt() very early after the kernel starts
executing.

File:
1 edited

Legend:

Unmodified
Added
Removed

  • kernel/arch/sparc64/src/mm/tlb.c

    ra5f76758 r10b890b  
    2727 */
    2828
    29  /** @addtogroup sparc64mm     
     29/** @addtogroup sparc64mm       
    3030 * @{
    3131 */
    … …  
    5858};
    5959
    60 /** Initialize ITLB and DTLB.
    61  *
    62  * The goal of this function is to disable MMU
    63  * so that both TLBs can be purged and new
    64  * kernel 4M locked entry can be installed.
    65  * After TLB is initialized, MMU is enabled
    66  * again.
    67  *
    68  * Switching MMU off imposes the requirement for
    69  * the kernel to run in identity mapped environment.
    70  */
    7160void tlb_arch_init(void)
    7261{
    73         tlb_tag_access_reg_t tag;
    74         tlb_data_t data;
    75         frame_address_t fr;
    76         page_address_t pg;
    77 
    78         fr.address = config.base;
    79         pg.address = config.base;
    80 
    81         immu_disable();
    82         dmmu_disable();
    83 
    84         /*
    85          * Demap everything, especially OpenFirmware.
    86          */
    87         itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);
    88         dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);
    89        
    90         /*
    91          * We do identity mapping of 4M-page at 4M.
    92          */
    93         tag.value = ASID_KERNEL;
    94         tag.vpn = pg.vpn;
    95 
    96         itlb_tag_access_write(tag.value);
    97         dtlb_tag_access_write(tag.value);
    98 
    99         data.value = 0;
    100         data.v = true;
    101         data.size = PAGESIZE_4M;
    102         data.pfn = fr.pfn;
    103         data.l = true;
    104         data.cp = 1;
    105         data.cv = 1;
    106         data.p = true;
    107         data.w = true;
    108         data.g = true;
    109 
    110         itlb_data_in_write(data.value);
    111         dtlb_data_in_write(data.value);
    112 
    113         /*
    114          * Register window traps can occur before MMU is enabled again.
    115          * This ensures that any such traps will be handled from
    116          * kernel identity mapped trap handler.
    117          */
    118         trap_switch_trap_table();
    119        
    120         tlb_invalidate_all();
    121 
    122         dmmu_enable();
    123         immu_enable();
    12462}
    12563
    … …  
    280218}
    281219
    282  /** @}
    283  */
    284 
     220/** @}
     221 */
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