Changeset 1ecdbb0 in mainline for kernel/arch/sparc64/include/barrier.h

Timestamp:

2006-12-14T21:19:37Z (18 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

771cd22

Parents:

9a8baed

Message:

Convert sparc64 critical section barriers to RMO memory model.
More portable, no confusion from documentation.

File:

• kernel/arch/sparc64/include/barrier.h (modified) (1 diff)

kernel/arch/sparc64/include/barrier.h

@@ -37 +37 @@
 
 /*
- * We assume TSO memory model in which only reads can pass earlier stores
- * (but not earlier reads). Therefore, CS_ENTER_BARRIER() and CS_LEAVE_BARRIER()
- * can be empty.
+ * Our critical section barriers are prepared for the weakest RMO memory model.
  */
-#define CS_ENTER_BARRIER()      __asm__ volatile ("" ::: "memory")
-#define CS_LEAVE_BARRIER()      __asm__ volatile ("" ::: "memory")
+#define CS_ENTER_BARRIER()                              \
+        __asm__ volatile (                              \
+                "membar #LoadLoad | #LoadStore\n"       \
+                ::: "memory"                            \
+        )
+#define CS_LEAVE_BARRIER()                              \
+        __asm__ volatile (                              \
+                "membar #StoreStore\n"                  \
+                "membar #LoadStore\n"                   \
+                ::: "memory"                            \
+        )
 
-#define memory_barrier()        __asm__ volatile ("membar #LoadLoad | #StoreStore\n" ::: "memory")
-#define read_barrier()          __asm__ volatile ("membar #LoadLoad\n" ::: "memory")
-#define write_barrier()         __asm__ volatile ("membar #StoreStore\n" ::: "memory")
+#define memory_barrier()        \
+        __asm__ volatile ("membar #LoadLoad | #StoreStore\n" ::: "memory")
+#define read_barrier()          \
+        __asm__ volatile ("membar #LoadLoad\n" ::: "memory")
+#define write_barrier()         \
+        __asm__ volatile ("membar #StoreStore\n" ::: "memory")
 
 /** Flush Instruction Memory instruction. */