Changeset 25d7709 in mainline for arch/ia64/src/mm/tlb.c


Ignore:
Timestamp:
2006-03-13T20:08:16Z (19 years ago)
Author:
Jakub Jermar <jakub@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
631ca4d
Parents:
45d6add
Message:

Nicer ia32 interrupt handlers and structures holding interrupted context data.
Unify the name holding interrupted context data on all architectures to be istate.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • arch/ia64/src/mm/tlb.c

    r45d6add r25d7709  
    443443 *
    444444 * @param vector Interruption vector.
    445  * @param pstate Structure with saved interruption state.
    446  */
    447 void alternate_instruction_tlb_fault(__u64 vector, struct exception_regdump *pstate)
     445 * @param istate Structure with saved interruption state.
     446 */
     447void alternate_instruction_tlb_fault(__u64 vector, istate_t *istate)
    448448{
    449449        region_register rr;
     
    451451        pte_t *t;
    452452       
    453         va = pstate->cr_ifa;    /* faulting address */
     453        va = istate->cr_ifa;    /* faulting address */
    454454        t = page_mapping_find(AS, va);
    455455        if (t) {
     
    464464                 */
    465465                if (!as_page_fault(va)) {
    466                         panic("%s: va=%P, rid=%d\n", __FUNCTION__, pstate->cr_ifa, rr.map.rid);
     466                        panic("%s: va=%P, rid=%d\n", __FUNCTION__, istate->cr_ifa, rr.map.rid);
    467467                }
    468468        }
     
    472472 *
    473473 * @param vector Interruption vector.
    474  * @param pstate Structure with saved interruption state.
    475  */
    476 void alternate_data_tlb_fault(__u64 vector, struct exception_regdump *pstate)
     474 * @param istate Structure with saved interruption state.
     475 */
     476void alternate_data_tlb_fault(__u64 vector, istate_t *istate)
    477477{
    478478        region_register rr;
     
    481481        pte_t *t;
    482482       
    483         va = pstate->cr_ifa;    /* faulting address */
     483        va = istate->cr_ifa;    /* faulting address */
    484484        rr.word = rr_read(VA2VRN(va));
    485485        rid = rr.map.rid;
     
    507507                 */
    508508                if (!as_page_fault(va)) {
    509                         panic("%s: va=%P, rid=%d\n", __FUNCTION__, pstate->cr_ifa, rr.map.rid);
     509                        panic("%s: va=%P, rid=%d\n", __FUNCTION__, istate->cr_ifa, rr.map.rid);
    510510                }
    511511        }
     
    517517 *
    518518 * @param vector Interruption vector.
    519  * @param pstate Structure with saved interruption state.
    520  */
    521 void data_nested_tlb_fault(__u64 vector, struct exception_regdump *pstate)
     519 * @param istate Structure with saved interruption state.
     520 */
     521void data_nested_tlb_fault(__u64 vector, istate_t *istate)
    522522{
    523523        panic("%s\n", __FUNCTION__);
     
    527527 *
    528528 * @param vector Interruption vector.
    529  * @param pstate Structure with saved interruption state.
    530  */
    531 void data_dirty_bit_fault(__u64 vector, struct exception_regdump *pstate)
     529 * @param istate Structure with saved interruption state.
     530 */
     531void data_dirty_bit_fault(__u64 vector, istate_t *istate)
    532532{
    533533        pte_t *t;
    534534
    535         t = page_mapping_find(AS, pstate->cr_ifa);
     535        t = page_mapping_find(AS, istate->cr_ifa);
    536536        ASSERT(t && t->p);
    537537        if (t && t->p) {
     
    548548 *
    549549 * @param vector Interruption vector.
    550  * @param pstate Structure with saved interruption state.
    551  */
    552 void instruction_access_bit_fault(__u64 vector, struct exception_regdump *pstate)
     550 * @param istate Structure with saved interruption state.
     551 */
     552void instruction_access_bit_fault(__u64 vector, istate_t *istate)
    553553{
    554554        pte_t *t;
    555555
    556         t = page_mapping_find(AS, pstate->cr_ifa);
     556        t = page_mapping_find(AS, istate->cr_ifa);
    557557        ASSERT(t && t->p);
    558558        if (t && t->p) {
     
    569569 *
    570570 * @param vector Interruption vector.
    571  * @param pstate Structure with saved interruption state.
    572  */
    573 void data_access_bit_fault(__u64 vector, struct exception_regdump *pstate)
     571 * @param istate Structure with saved interruption state.
     572 */
     573void data_access_bit_fault(__u64 vector, istate_t *istate)
    574574{
    575575        pte_t *t;
    576576
    577         t = page_mapping_find(AS, pstate->cr_ifa);
     577        t = page_mapping_find(AS, istate->cr_ifa);
    578578        ASSERT(t && t->p);
    579579        if (t && t->p) {
     
    590590 *
    591591 * @param vector Interruption vector.
    592  * @param pstate Structure with saved interruption state.
    593  */
    594 void page_not_present(__u64 vector, struct exception_regdump *pstate)
     592 * @param istate Structure with saved interruption state.
     593 */
     594void page_not_present(__u64 vector, istate_t *istate)
    595595{
    596596        region_register rr;
     
    598598        pte_t *t;
    599599       
    600         va = pstate->cr_ifa;    /* faulting address */
     600        va = istate->cr_ifa;    /* faulting address */
    601601        t = page_mapping_find(AS, va);
    602602        ASSERT(t);
     
    613613        } else {
    614614                if (!as_page_fault(va)) {
    615                         panic("%s: va=%P, rid=%d\n", __FUNCTION__, pstate->cr_ifa, rr.map.rid);
    616                 }
    617         }
    618 }
     615                        panic("%s: va=%P, rid=%d\n", __FUNCTION__, istate->cr_ifa, rr.map.rid);
     616                }
     617        }
     618}
Note: See TracChangeset for help on using the changeset viewer.