Changeset 281b607 in mainline


Ignore:
Timestamp:
2006-03-23T10:29:39Z (19 years ago)
Author:
Ondrej Palkovsky <ondrap@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
a0bb10ef
Parents:
9aa72b4
Message:

Added basic kernel infrastructure for ThreadLocalStorage(TLS) for
ia32(complete),amd64(complete),mips32(missing emulation of rdhwr instruction).

Files:
13 edited

Legend:

Unmodified
Added
Removed

  • arch/amd64/include/cpu.h

    r9aa72b4 r281b607  
    4343#define AMD_MSR_LSTAR   0xc0000082
    4444#define AMD_MSR_SFMASK  0xc0000084
     45#define AMD_MSR_FS      0xc0000100
    4546#define AMD_MSR_GS      0xc0000101
    4647

  • arch/amd64/include/thread.h

    r9aa72b4 r281b607  
    3030#define __amd64_THREAD_H__
    3131
    32 #define ARCH_THREAD_DATA
     32#define ARCH_THREAD_DATA __native tls;
    3333
    3434#endif

  • arch/amd64/src/amd64.c

    r9aa72b4 r281b607  
    3333#include <config.h>
    3434
     35#include <proc/thread.h>
    3536#include <arch/ega.h>
    3637#include <genarch/i8042/i8042.h>
    … …  
    4849#include <arch/syscall.h>
    4950#include <arch/debugger.h>
     51#include <syscall/syscall.h>
     52
    5053
    5154/** Disable I/O on non-privileged levels
    … …  
    160163        i8254_normal_operation();
    161164}
     165
     166/** Set Thread-local-storeage pointer
     167 *
     168 * TLS pointer is set in FS register. Unfortunately the 64-bit
     169 * part can be set only in CPL0 mode.
     170 *
     171 * The specs says, that on %fs:0 there is stored contents of %fs register,
     172 * we need not to go to CPL0 to read it.
     173 */
     174__native sys_tls_set(__native addr)
     175{
     176        THREAD->tls = addr;
     177        write_msr(AMD_MSR_FS, addr);
     178        return 0;
     179}

  • arch/amd64/src/proc/scheduler.c

    r9aa72b4 r281b607  
    4646        swapgs();
    4747
     48        /* TLS support - set FS to thread local storage */
     49        write_msr(AMD_MSR_FS, THREAD->tls);
     50
    4851#ifdef CONFIG_DEBUG_AS_WATCHPOINT
    4952        /* Set watchpoint on AS to ensure that nobody sets it to zero */

  • arch/ia32/include/pm.h

    r9aa72b4 r281b607  
    3131
    3232#define IDT_ITEMS 64
    33 #define GDT_ITEMS 6
     33#define GDT_ITEMS 7
    3434
    3535#define NULL_DES        0
    … …  
    3939#define UDATA_DES       4
    4040#define TSS_DES         5
     41#define TLS_DES         6 /* Pointer to Thread-Local-Storage data */
    4142
    4243#define selector(des)   ((des)<<3)
    … …  
    147148
    148149extern void tss_initialize(struct tss *t);
     150extern void set_tls_desc(__address tls);
    149151
    150152#endif /* __ASM__ */

  • arch/ia32/include/thread.h

    r9aa72b4 r281b607  
    3030#define __ia32_THREAD_H__
    3131
    32 #define ARCH_THREAD_DATA
     32#define ARCH_THREAD_DATA __native tls;
    3333
    3434#endif

  • arch/ia32/src/ia32.c

    r9aa72b4 r281b607  
    5252#include <interrupt.h>
    5353#include <arch/debugger.h>
     54#include <proc/thread.h>
     55#include <syscall/syscall.h>
    5456
    5557void arch_pre_mm_init(void)
    … …  
    107109        }
    108110}
     111
     112/** Set Thread-local-storeage pointer
     113 *
     114 * TLS pointer is set in FS register. Unfortunately the 64-bit
     115 * part can be set only in CPL0 mode.
     116 *
     117 * The specs says, that on %fs:0 there is stored contents of %fs register,
     118 * we need not to go to CPL0 to read it.
     119 */
     120__native sys_tls_set(__native addr)
     121{
     122        THREAD->tls = addr;
     123        set_tls_desc(addr);
     124
     125        return 0;
     126}

  • arch/ia32/src/pm.c

    r9aa72b4 r281b607  
    4949 * mode, we use, for each privilege level, two segments spanning the
    5050 * whole memory. One is for code and one is for data.
     51 *
     52 * One is for GS register which holds pointer to the TLS thread
     53 * structure in it's base.
    5154 */
    5255struct descriptor gdt[GDT_ITEMS] = {
    … …  
    6265        { 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER, 0xf, 0, 0, 1, 1, 0 },
    6366        /* TSS descriptor - set up will be completed later */
    64         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
     67        { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     68        { 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER, 0xf, 0, 0, 1, 1, 0 }
    6569};
    6670
    … …  
    215219        clean_AM_flag();          /* Disable alignment check */
    216220}
     221
     222void set_tls_desc(__address tls)
     223{
     224        struct ptr_16_32 cpugdtr;
     225        struct descriptor *gdt_p = (struct descriptor *) cpugdtr.base;
     226
     227        __asm__ volatile ("sgdt %0\n" : : "m" (cpugdtr));
     228
     229        gdt_setbase(&gdt_p[TLS_DES], tls);
     230        /* Reload gdt register to update GS in CPU */
     231        __asm__ volatile ("lgdt %0\n" : : "m" (cpugdtr));
     232}

  • arch/ia32/src/proc/scheduler.c

    r9aa72b4 r281b607  
    3333#include <arch/context.h>       /* SP_DELTA */
    3434#include <arch/debugger.h>
     35#include <arch/pm.h>
    3536
    3637void before_thread_runs_arch(void)
    … …  
    3839        CPU->arch.tss->esp0 = (__address) &THREAD->kstack[THREAD_STACK_SIZE-SP_DELTA];
    3940        CPU->arch.tss->ss0 = selector(KDATA_DES);
     41
     42        /* Set up TLS in GS register */
     43        set_tls_desc(THREAD->tls);
    4044
    4145#ifdef CONFIG_DEBUG_AS_WATCHPOINT

  • arch/ia32/src/userspace.c

    r9aa72b4 r281b607  
    5656                "popfl\n"
    5757
     58                /* Set up GS register (TLS) */
     59                "movl %6, %%gs\n"
     60
    5861                "pushl %0\n"
    5962                "pushl %1\n"
    … …  
    6669                : "i" (selector(UDATA_DES) | PL_USER), "r" (kernel_uarg->uspace_stack+THREAD_STACK_SIZE),
    6770                  "r" (ipl), "i" (selector(UTEXT_DES) | PL_USER), "r" (kernel_uarg->uspace_entry),
    68                   "r" (kernel_uarg->uspace_uarg)
     71                "r" (kernel_uarg->uspace_uarg),
     72                "r" (selector(TLS_DES))
    6973                : "eax");
    7074       

  • arch/mips32/src/mips32.c

    r9aa72b4 r281b607  
    4040#include <proc/uarg.h>
    4141#include <print.h>
     42#include <syscall/syscall.h>
    4243
    4344#include <arch/interrupt.h>
    … …  
    142143{
    143144}
     145
     146/** Set Thread-local-storeage pointer
     147 *
     148 * We have it currently in K1, it is
     149 * possible to have it separately in the future.
     150 */
     151__native sys_tls_set(__native addr)
     152{
     153        return 0;
     154}

  • generic/include/syscall/syscall.h

    r9aa72b4 r281b607  
    3232typedef enum {
    3333        SYS_IO = 0,
     34        SYS_TLS_SET = 1, /* Hardcoded in AMD64,IA32 uspace - psthread.S */
    3435        SYS_THREAD_CREATE,
    3536        SYS_THREAD_EXIT,
    … …  
    6061extern __native syscall_handler(__native a1, __native a2, __native a3,
    6162                                __native a4, __native id);
     63extern __native sys_tls_set(__native addr);
     64
    6265
    6366#endif

  • generic/src/syscall/syscall.c

    r9aa72b4 r281b607  
    7676syshandler_t syscall_table[SYSCALL_END] = {
    7777        sys_io,
     78        sys_tls_set,
    7879        sys_thread_create,
    7980        sys_thread_exit,
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