Ignore:
Timestamp:
2006-09-18T22:10:20Z (18 years ago)
Author:
Jakub Jermar <jakub@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
19dba2b
Parents:
57da95c
Message:

sparc64 work:

  • Experimental support for TSB (Translation Storage Buffer).
File:
1 edited

Legend:

Unmodified
Added
Removed

  • kernel/arch/sparc64/include/barrier.h

    r57da95c r29b2bbf  
    4242#define CS_LEAVE_BARRIER()      __asm__ volatile ("" ::: "memory")
    4343
    44 #define memory_barrier()
    45 #define read_barrier()
    46 #define write_barrier()
     44#define memory_barrier()        __asm__ volatile ("membar #LoadLoad | #StoreStore\n" ::: "memory")
     45#define read_barrier()          __asm__ volatile ("membar #LoadLoad\n" ::: "memory")
     46#define write_barrier()         __asm__ volatile ("membar #StoreStore\n" ::: "memory")
    4747
    4848/** Flush Instruction Memory instruction. */
Note: See TracChangeset for help on using the changeset viewer.