Changeset 49a736e2 in mainline for boot/arch/arm32/src/mm.c
- Timestamp:
- 2012-04-11T16:18:43Z (13 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 179f6f2
- Parents:
- c127e1c
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
boot/arch/arm32/src/mm.c
rc127e1c r49a736e2 107 107 "mcr p15, 0, r0, c3, c0, 0\n" 108 108 109 #ifdef PROCESSOR_armv7 110 /* Clean L2 cache */ 111 "mov r12, #0x1\n" //set up to invalidate L2 112 "smc #0\n" //Call SMI monitor 113 109 #ifdef PROCESSOR_armv7_a 114 110 /* Read Auxiliary control register */ 115 111 "mrc p15, 0, r0, c1, c0, 1\n" … … 123 119 "mrc p15, 0, r0, c1, c0, 0\n" 124 120 125 #ifdef PROCESSOR_armv7 121 #ifdef PROCESSOR_armv7_a 126 122 /* Mask to enable paging, alignment and caching */ 127 123 "ldr r1, =0x00000007\n"
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