Changeset 52fc805 in mainline


Ignore:
Timestamp:
2012-10-15T19:27:58Z (12 years ago)
Author:
Jan Vesely <jano.vesely@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
a5a73c0
Parents:
f4c9e42
Message:

rootamdm37x: Use new pio functions to access UHH and TLL

Location:
uspace/drv/infrastructure/rootamdm37x
Files:
3 edited

Legend:

Unmodified
Added
Removed

  • uspace/drv/infrastructure/rootamdm37x/rootamdm37x.c

    rf4c9e42 r52fc805  
    164164
    165165        /* Reset USB TLL */
    166         device->tll->sysconfig |= TLL_SYSCONFIG_SOFTRESET_FLAG;
     166        pio_set_32(&device->tll->sysconfig, TLL_SYSCONFIG_SOFTRESET_FLAG, 5);
    167167        ddf_msg(LVL_DEBUG2, "Waiting for USB TLL reset");
    168         while (!(device->tll->sysstatus & TLL_SYSSTATUS_RESET_DONE_FLAG));
     168        while (!(pio_read_32(&device->tll->sysstatus) & TLL_SYSSTATUS_RESET_DONE_FLAG));
    169169        ddf_msg(LVL_DEBUG, "USB TLL Reset done.");
    170170
    171         {
    172171        /* Setup idle mode (smart idle) */
    173         uint32_t sysc = device->tll->sysconfig;
    174         sysc |= TLL_SYSCONFIG_CLOCKACTIVITY_FLAG | TLL_SYSCONFIG_AUTOIDLE_FLAG;
    175         sysc = (sysc
    176             & ~(TLL_SYSCONFIG_SIDLE_MODE_MASK << TLL_SYSCONFIG_SIDLE_MODE_SHIFT)
    177             ) | (0x2 << TLL_SYSCONFIG_SIDLE_MODE_SHIFT);
    178         device->tll->sysconfig = sysc;
    179         ddf_msg(LVL_DEBUG2, "Set TLL->sysconfig (%p) to %x:%x.",
    180             &device->tll->sysconfig, device->tll->sysconfig, sysc);
    181         }
    182 
    183         {
     172        pio_change_32(&device->tll->sysconfig,
     173            TLL_SYSCONFIG_CLOCKACTIVITY_FLAG | TLL_SYSCONFIG_AUTOIDLE_FLAG |
     174            TLL_SYSCONFIG_SIDLE_MODE_SMART, TLL_SYSCONFIG_SIDLE_MODE_MASK, 5);
     175
    184176        /* Smart idle for UHH */
    185         uint32_t sysc = device->uhh->sysconfig;
    186         sysc |= UHH_SYSCONFIG_CLOCKACTIVITY_FLAG | UHH_SYSCONFIG_AUTOIDLE_FLAG;
    187         sysc = (sysc
    188             & ~(UHH_SYSCONFIG_SIDLE_MODE_MASK << UHH_SYSCONFIG_SIDLE_MODE_SHIFT)
    189             ) | (0x2 << UHH_SYSCONFIG_SIDLE_MODE_SHIFT);
    190         sysc = (sysc
    191             & ~(UHH_SYSCONFIG_MIDLE_MODE_MASK << UHH_SYSCONFIG_MIDLE_MODE_SHIFT)
    192             ) | (0x2 << UHH_SYSCONFIG_MIDLE_MODE_SHIFT);
    193         ddf_msg(LVL_DEBUG2, "Set UHH->sysconfig (%p) to %x.",
    194             &device->uhh->sysconfig, device->uhh->sysconfig);
    195         device->uhh->sysconfig = sysc;
    196 
    197         /* All ports are connected on BBxM */
    198         device->uhh->hostconfig |= (UHH_HOSTCONFIG_P1_CONNECT_STATUS_FLAG
    199             | UHH_HOSTCONFIG_P2_CONNECT_STATUS_FLAG
    200             | UHH_HOSTCONFIG_P3_CONNECT_STATUS_FLAG);
     177        pio_change_32(&device->uhh->sysconfig,
     178            UHH_SYSCONFIG_CLOCKACTIVITY_FLAG | UHH_SYSCONFIG_AUTOIDLE_FLAG |
     179            UHH_SYSCONFIG_SIDLE_MODE_SMART, UHH_SYSCONFIG_SIDLE_MODE_MASK, 5);
    201180
    202181        /* Set all ports to go through TLL(UTMI)
    203182         * Direct connection can only work in HS mode */
    204         device->uhh->hostconfig |= (UHH_HOSTCONFIG_P1_ULPI_BYPASS_FLAG
    205             | UHH_HOSTCONFIG_P2_ULPI_BYPASS_FLAG
    206             | UHH_HOSTCONFIG_P3_ULPI_BYPASS_FLAG);
    207         ddf_msg(LVL_DEBUG2, "Set UHH->hostconfig (%p) to %x.",
    208             &device->uhh->hostconfig, device->uhh->hostconfig);
    209         }
    210 
    211         device->tll->shared_conf |= TLL_SHARED_CONF_FCLK_IS_ON_FLAG;
    212         ddf_msg(LVL_DEBUG2, "Set shared conf port (%p) to %x.",
    213             &device->tll->shared_conf, device->tll->shared_conf);
     183        pio_set_32(&device->uhh->hostconfig,
     184            UHH_HOSTCONFIG_P1_ULPI_BYPASS_FLAG |
     185            UHH_HOSTCONFIG_P2_ULPI_BYPASS_FLAG |
     186            UHH_HOSTCONFIG_P3_ULPI_BYPASS_FLAG, 5);
     187
     188        /* What is this? */
     189        pio_set_32(&device->tll->shared_conf, TLL_SHARED_CONF_FCLK_IS_ON_FLAG, 5);
    214190
    215191        for (unsigned i = 0; i < 3; ++i) {
    216                 uint32_t ch = device->tll->channel_conf[i];
    217                 /* Clear Channel mode and FSLS mode */
    218                 ch &= ~(TLL_CHANNEL_CONF_CHANMODE_MASK
    219                     << TLL_CHANNEL_CONF_CHANMODE_SHIFT)
    220                     & ~(TLL_CHANNEL_CONF_FSLSMODE_MASK
    221                     << TLL_CHANNEL_CONF_FSLSMODE_SHIFT);
    222 
    223                 /* Serial mode is the only one capable of FS/LS operation. */
    224                 ch |= (TLL_CHANNEL_CONF_CHANMODE_UTMI_SERIAL_MODE
    225                     << TLL_CHANNEL_CONF_CHANMODE_SHIFT);
    226 
    227                 /* Select FS/LS mode, no idea what the difference is
     192                /* Serial mode is the only one capable of FS/LS operation.
     193                 * Select FS/LS mode, no idea what the difference is
    228194                 * one of bidirectional modes might be good choice
    229195                 * 2 = 3pin bidi phy. */
    230                 ch |= (2 << TLL_CHANNEL_CONF_FSLSMODE_SHIFT);
    231 
    232                 /* Write to register */
    233                 ddf_msg(LVL_DEBUG2, "Setting port %u(%p) to %x.",
    234                     i, &device->tll->channel_conf[i], ch);
    235                 device->tll->channel_conf[i] = ch;
     196                pio_change_32(&device->tll->channel_conf[i],
     197                    TLL_CHANNEL_CONF_CHANMODE_UTMI_SERIAL_MODE |
     198                    TLL_CHANNEL_CONF_FSLSMODE_3PIN_BIDI_PHY,
     199                    TLL_CHANNEL_CONF_CHANMODE_MASK |
     200                    TLL_CHANNEL_CONF_FSLSMODE_MASK, 5);
    236201        }
    237202        return EOK;

  • uspace/drv/infrastructure/rootamdm37x/uhh.h

    rf4c9e42 r52fc805  
    4242typedef struct {
    4343        const ioport32_t revision;
    44 #define UHH_REVISION_MASK  0xf
    45 #define UHH_REVISION_MINOR_SHIFT  0
    46 #define UHH_REVISION_MAJOR_SHIFT  4
     44#define UHH_REVISION_MINOR_MASK  0x0f
     45#define UHH_REVISION_MAJOR_MASK  0xf0
    4746
    4847        uint32_t padd0_[3];
    … …  
    5150#define UHH_SYSCONFIG_SOFTRESET_FLAG  (1 << 1)
    5251#define UHH_SYSCONFIG_ENWAKEUP_FLAG  (1 << 2)
     52#define UHH_SYSCONFIG_SIDLE_MODE_MASK  (0x3 << 3)
     53#define UHH_SYSCONFIG_SIDLE_MODE_FORCE  (0x0 << 3)
     54#define UHH_SYSCONFIG_SIDLE_MODE_NO  (0x1 << 3)
     55#define UHH_SYSCONFIG_SIDLE_MODE_SMART  (0x2 << 3)
    5356#define UHH_SYSCONFIG_CLOCKACTIVITY_FLAG  (1 << 8)
    54 #define UHH_SYSCONFIG_SIDLE_MODE_MASK  0x3
    55 #define UHH_SYSCONFIG_SIDLE_MODE_SHIFT  3
    56 #define UHH_SYSCONFIG_MIDLE_MODE_MASK  0x3
    57 #define UHH_SYSCONFIG_MIDLE_MODE_SHIFT  12
     57#define UHH_SYSCONFIG_MIDLE_MODE_MASK  (0x3 << 12)
     58#define UHH_SYSCONFIG_MIDLE_MODE_FORCE  (0x0 << 12)
     59#define UHH_SYSCONFIG_MIDLE_MODE_NO  (0x1 << 12)
     60#define UHH_SYSCONFIG_MIDLE_MODE_SMART  (0x2 << 12)
    5861
    5962        const ioport32_t sysstatus;
    … …  
    7780
    7881        ioport32_t debug_csr;
    79 #define UHH_DEBUG_CSR_EHCI_FLADJ_MASK  (0x3f)
    80 #define UHH_DEBUG_CSR_EHCI_FLADJ_SHIFT  0
     82#define UHH_DEBUG_CSR_EHCI_FLADJ_MASK  (0x3f << 0)
     83#define UHH_DEBUG_CSR_EHCI_FLADJ(x)  ((x) & 0x3f)
    8184#define UHH_DEBUG_CSR_EHCI_SIMULATION_MODE_FLAG  (1 << 6)
    8285#define UHH_DEBUG_CSR_OHCI_CNTSEL_FLAG  (1 << 7)

  • uspace/drv/infrastructure/rootamdm37x/usbtll.h

    rf4c9e42 r52fc805  
    4242typedef struct {
    4343        const ioport32_t revision;
    44 #define TLL_REVISION_MASK  0xf
    45 #define TLL_REVISION_MINOR_SHIFT  0
    46 #define TLL_REVISION_MAJOR_SHIFT  4
     44#define TLL_REVISION_MINOR_MASK  0x0f
     45#define TLL_REVISION_MAJOR_MASK  0xf0
    4746
    4847        uint32_t padd0_[3];
    … …  
    5150#define TLL_SYSCONFIG_SOFTRESET_FLAG  (1 << 1)
    5251#define TLL_SYSCONFIG_ENWAKEUP_FLAG  (1 << 2)
     52#define TLL_SYSCONFIG_SIDLE_MODE_MASK  (0x3 << 3)
     53#define TLL_SYSCONFIG_SIDLE_MODE_FORCE  (0x0 << 3)
     54#define TLL_SYSCONFIG_SIDLE_MODE_NO  (0x1 << 3)
     55#define TLL_SYSCONFIG_SIDLE_MODE_SMART  (0x2 << 3)
    5356#define TLL_SYSCONFIG_CLOCKACTIVITY_FLAG  (1 << 8)
    54 #define TLL_SYSCONFIG_SIDLE_MODE_MASK  0x3
    55 #define TLL_SYSCONFIG_SIDLE_MODE_SHIFT  3
    5657
    5758        ioport32_t sysstatus;
    … …  
    7273#define TLL_SHARED_CONF_FCLK_IS_ON_FLAG  (1 << 0)
    7374#define TLL_SHARED_CONF_FCLK_REQ_FLAG  (1 << 1)
     75#define TLL_SHARED_CONF_USB_DIVRATIO_MASK  (0x7 << 2)
     76#define TLL_SHARED_CONF_USB_DIVRATIO(x)  (((x) & 0x7) << 2)
    7477#define TLL_SHARED_CONF_USB_180D_SDR_EN_FLAG  (1 << 5)
    7578#define TLL_SHARED_CONF_USB_90D_DDR_EN_FLAG  (1 << 6)
    76 #define TLL_SHARED_CONF_USB_DIVRATIO_MASK  0x7
    77 #define TLL_SHARED_CONF_USB_DIVRATIO_SHIFT 2
    7879
    7980        uint32_t padd2_[3];
    8081        ioport32_t channel_conf[3];
    8182#define TLL_CHANNEL_CONF_CHANEN_FLAG  (1 << 0)
    82 #define TLL_CHANNEL_CONF_CHANMODE_MASK  0x3
    83 #define TLL_CHANNEL_CONF_CHANMODE_SHIFT  1
    84 #define TLL_CHANNEL_CONF_CHANMODE_UTMI_ULPI_MODE 0
    85 #define TLL_CHANNEL_CONF_CHANMODE_UTMI_SERIAL_MODE 1
    86 #define TLL_CHANNEL_CONF_CHANMODE_UTMI_TRANS_MODE 2
    87 #define TLL_CHANNEL_CONF_CHANMODE_NO_MODE 3
     83#define TLL_CHANNEL_CONF_CHANMODE_MASK  (0x3 << 1)
     84#define TLL_CHANNEL_CONF_CHANMODE_UTMI_ULPI_MODE (0x0 << 1)
     85#define TLL_CHANNEL_CONF_CHANMODE_UTMI_SERIAL_MODE (0x1 << 1)
     86#define TLL_CHANNEL_CONF_CHANMODE_UTMI_TRANS_MODE (0x2 << 1)
     87#define TLL_CHANNEL_CONF_CHANMODE_NO_MODE (0x3 << 1)
    8888#define TLL_CHANNEL_CONF_UTMIISADEV_FLAG  (1 << 3)
    8989#define TLL_CHANNEL_CONF_TLLATTACH_FLAG  (1 << 4)
    … …  
    101101#define TLL_CHANNEL_CONF_TESTTXDAT_FLAG  (1 << 19)
    102102#define TLL_CHANNEL_CONF_TESTTXSE0_FLAG  (1 << 20)
    103 #define TLL_CHANNEL_CONF_FSLSMODE_MASK  0xf
    104 #define TLL_CHANNEL_CONF_FSLSMODE_SHIFT  24
    105 #define TLL_CHANNEL_CONF_FSLSLINESTATE_MASK  0x3
    106 #define TLL_CHANNEL_CONF_FSLSLINESTATE_SHIFT  28
     103#define TLL_CHANNEL_CONF_FSLSMODE_MASK   (0xf << 24)
     104#define TLL_CHANNEL_CONF_FSLSMODE_6PIN_UNI_PHY_TX_DATSE0   (0x0 << 24)
     105#define TLL_CHANNEL_CONF_FSLSMODE_6PIN_UNI_PHY_TX_DPDM   (0x1 << 24)
     106#define TLL_CHANNEL_CONF_FSLSMODE_3PIN_BIDI_PHY   (0x2 << 24)
     107#define TLL_CHANNEL_CONF_FSLSMODE_4PIN_BIDI_PHY   (0x3 << 24)
     108#define TLL_CHANNEL_CONF_FSLSMODE_6PIN_UNI_TLL_TX_DATSE0  (0x4 << 24)
     109#define TLL_CHANNEL_CONF_FSLSMODE_6PIN_UNI_TLL_TX_DPDM  (0x5 << 24)
     110#define TLL_CHANNEL_CONF_FSLSMODE_3PIN_BIDI_TLL  (0x6 << 24)
     111#define TLL_CHANNEL_CONF_FSLSMODE_4PIN_BIDI_TLL  (0x7 << 24)
     112#define TLL_CHANNEL_CONF_FSLSMODE_2PIN_BIDI_TLL_DATSE0  (0xa << 24)
     113#define TLL_CHANNEL_CONF_FSLSMODE_2PIN_BIDI_TLL_DPDM  (0xb << 24)
     114
     115#define TLL_CHANNEL_CONF_FSLSLINESTATE_MASK  (0x3 << 28)
     116#define TLL_CHANNEL_CONF_FSLSLINESTATE_SE0  (0x0 << 28)
     117#define TLL_CHANNEL_CONF_FSLSLINESTATE_FS_J  (0x1 << 28)
     118#define TLL_CHANNEL_CONF_FSLSLINESTATE_FS_K  (0x2 << 28)
     119#define TLL_CHANNEL_CONF_FSLSLINESTATE_SE1  (0x3 << 28)
    107120
    108121        /* The rest are 8bit ULPI registers */
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