Changeset 5856b627 in mainline for kernel/arch/arm32/src/cpu/cpu.c

Timestamp:

2013-08-20T12:36:48Z (12 years ago)

Author:

Jan Vesely <jano.vesely@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

26e2de3

Parents:

0ee999d (diff), 4da8fdb (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.

Message:

Mainline changes.

File:

• kernel/arch/arm32/src/cpu/cpu.c (modified) (8 diffs)

kernel/arch/arm32/src/cpu/cpu.c

@@ -157 +157 @@
 #endif
 #ifdef PROCESSOR_ARCH_armv7_a
-         /* ICache coherency is elaborate on in barrier.h.
+         /* ICache coherency is elaborated on in barrier.h.
           * VIPT and PIPT caches need maintenance only on code modify,
           * so it should be safe for general use.
@@ -166 +166 @@
                 control_reg |=
                     SCTLR_INST_CACHE_EN_FLAG | SCTLR_BRANCH_PREDICT_EN_FLAG;
+        } else {
+                control_reg &=
+                    ~(SCTLR_INST_CACHE_EN_FLAG | SCTLR_BRANCH_PREDICT_EN_FLAG);
         }
 #endif
@@ -204 +207 @@
 #ifdef PROCESSOR_ARCH_armv7_a
         CSSELR_write((level & CCSELR_LEVEL_MASK) << CCSELR_LEVEL_SHIFT);
-        const unsigned ls_log = 2 +
-            ((CCSIDR_read() >> CCSIDR_LINESIZE_SHIFT) & CCSIDR_LINESIZE_MASK);
-        return ls_log + 2; //return log2(bytes)
+        const uint32_t ccsidr = CCSIDR_read();
+        return CCSIDR_LINESIZE_LOG(ccsidr);
 #endif
         return 0;
@@ -217 +219 @@
 #ifdef PROCESSOR_ARCH_armv7_a
         CSSELR_write((level & CCSELR_LEVEL_MASK) << CCSELR_LEVEL_SHIFT);
-        const unsigned ways = 1 +
-            ((CCSIDR_read() >> CCSIDR_ASSOC_SHIFT) & CCSIDR_ASSOC_MASK);
-        return ways;
+        const uint32_t ccsidr = CCSIDR_read();
+        return CCSIDR_WAYS(ccsidr);
 #endif
         return 0;
@@ -229 +230 @@
 #ifdef PROCESSOR_ARCH_armv7_a
         CSSELR_write((level & CCSELR_LEVEL_MASK) << CCSELR_LEVEL_SHIFT);
-        const unsigned sets = 1 +
-            ((CCSIDR_read() >> CCSIDR_NUMSETS_SHIFT) & CCSIDR_NUMSETS_MASK);
-        return sets;
+        const uint32_t ccsidr = CCSIDR_read();
+        return CCSIDR_SETS(ccsidr);
 #endif
         return 0;
@@ -241 +241 @@
 #ifdef PROCESSOR_ARCH_armv7_a
         const uint32_t val = CLIDR_read();
-        for (unsigned i = 1; i <= 7; ++i) {
+        for (unsigned i = 0; i < 8; ++i) {
                 const unsigned ctype = CLIDR_CACHE(i, val);
                 switch (ctype) {
@@ -280 +280 @@
                 const unsigned ways = dcache_ways(i);
                 const unsigned sets = dcache_sets(i);
-                const unsigned way_shift =  31 - log2(ways);
+                const unsigned way_shift = 32 - log2(ways);
                 const unsigned set_shift = dcache_linesize_log(i);
                 dcache_clean_manual(i, false, ways, sets, way_shift, set_shift);
@@ -293 +293 @@
                 const unsigned ways = dcache_ways(i);
                 const unsigned sets = dcache_sets(i);
-                const unsigned way_shift =  31 - log2(ways);
+                const unsigned way_shift = 32 - log2(ways);
                 const unsigned set_shift = dcache_linesize_log(i);
                 dcache_clean_manual(i, true, ways, sets, way_shift, set_shift);