Changeset 7c3fb9b in mainline for boot/arch/arm32/src/mm.c
- Timestamp:
- 2018-05-17T08:29:01Z (7 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 6ff23ff
- Parents:
- fac0ac7
- git-author:
- Jiri Svoboda <jiri@…> (2018-05-16 17:28:17)
- git-committer:
- Jiri Svoboda <jiri@…> (2018-05-17 08:29:01)
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
boot/arch/arm32/src/mm.c
rfac0ac7 r7c3fb9b 210 210 "mrc p15, 0, r0, c1, c0, 0\n" 211 211 212 /* Enable ICache, DCache, BPredictors and MMU, 212 /* 213 * Enable ICache, DCache, BPredictors and MMU, 213 214 * we disable caches before jumping to kernel 214 215 * so this is safe for all archs. … … 224 225 "orr r0, r0, r1\n" 225 226 226 /* Invalidate the TLB content before turning on the MMU. 227 /* 228 * Invalidate the TLB content before turning on the MMU. 227 229 * ARMv7-A Reference manual, B3.10.3 228 230 */ … … 240 242 disable_paging(); 241 243 #ifdef PROCESSOR_ARCH_armv7_a 242 /* Make sure we run in memory code when caches are enabled, 244 /* 245 * Make sure we run in memory code when caches are enabled, 243 246 * make sure we read memory data too. This part is ARMv7 specific as 244 247 * ARMv7 no longer invalidates caches on restart. 245 * See chapter B2.2.2 of ARM Architecture Reference Manual p. B2-1263*/ 248 * See chapter B2.2.2 of ARM Architecture Reference Manual p. B2-1263 249 */ 246 250 cache_invalidate(); 247 251 #endif
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