Changeset b5e0bb8 in mainline for arch/sparc64/include/mm/mmu.h

Timestamp:

2006-02-01T23:06:10Z (19 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

4e147a6

Parents:

071a8ae6

Message:

sparc64 bugfix.
When disabling IMMU and DMMU the kernel has to perform synchronization operation
(e.g flush %r or membar #Sync instruction). There is no guarantee that the address
contained in %r is in DTLB and therefore the flush instruction can fault. Normally
this would be recognized and fixed by the OpenFirmware Fast Data MMU fault handler.
However, this handler lives in virtually mapped memory and an attempt to execute
there while the MMUs are disabled would result in a nested trap leading to error state.
Replacing flush %r instruction with membar #Sync, wich is sufficient in this case,
fixes this problem.

File:

• arch/sparc64/include/mm/mmu.h (modified) (2 diffs)

arch/sparc64/include/mm/mmu.h

@@ -111 +111 @@
         cr.im = enable;
         asi_u64_write(ASI_LSU_CONTROL_REG, 0, cr.value);
-        flush();
+        membar();
 }
 
@@ -122 +122 @@
         cr.dm = enable;
         asi_u64_write(ASI_LSU_CONTROL_REG, 0, cr.value);
-        flush();
+        membar();
 }