Changeset d0780b4c in mainline

Timestamp:

2006-01-29T19:55:08Z (19 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

df09142f

Parents:

457d18a

Message:

ia32 SMP updates.
Update info about supported version of Bochs (bump the counter to 2.2.6).
Add Task Priority Register type and initialize this register to a known state.

Files:

• arch/ia32/include/smp/apic.h (modified) (2 diffs)
• arch/ia32/src/smp/apic.c (modified) (4 diffs)
• doc/arch/amd64 (modified) (1 diff)
• doc/arch/ia32 (modified) (1 diff)

arch/ia32/include/smp/apic.h

@@ -152 +152 @@
 /* Task Priority Register */
 #define TPR             (0x080/sizeof(__u32))
-#define TPRClear        0xffffff00
+union tpr {
+        __u32 value;
+        struct {
+                unsigned pri_sc : 4;            /**< Task Priority Sub-Class. */
+                unsigned pri : 4;               /**< Task Priority. */
+        } __attribute__ ((packed));
+};
+typedef union tpr tpr_t;
 
 /** Spurious-Interrupt Vector Register. */
@@ -159 +166 @@
         __u32 value;
         struct {
-                __u8 vector;                    /**< Spurious Vector */
-                unsigned lapic_enabled : 1;     /**< APIC Software Enable/Disable */
-                unsigned focus_checking : 1;    /**< Focus Processor Checking */
+                __u8 vector;                    /**< Spurious Vector. */
+                unsigned lapic_enabled : 1;     /**< APIC Software Enable/Disable. */
+                unsigned focus_checking : 1;    /**< Focus Processor Checking. */
                 unsigned : 22;                  /**< Reserved. */
         } __attribute__ ((packed));

arch/ia32/src/smp/apic.c

@@ -45 +45 @@
  * Advanced Programmable Interrupt Controller for SMP systems.
  * Tested on:
- *      Bochs 2.0.2 - Bochs 2.2.5 with 2-8 CPUs
+ *      Bochs 2.0.2 - Bochs 2.2.6 with 2-8 CPUs
  *      Simics 2.0.28 - Simics 2.2.19 2-15 CPUs
  *      VMware Workstation 5.5 with 2 CPUs
@@ -309 +309 @@
         lvt_error_t error;
         lvt_lint_t lint;
+        tpr_t tpr;
         svr_t svr;
         icr_t icr;
@@ -331 +332 @@
         lint.masked = true;
         l_apic[LVT_LINT1] = lint.value;
+
+        /* Task Priority Register initialization. */
+        tpr.value = l_apic[TPR];
+        tpr.pri_sc = 0;
+        tpr.pri = 0;
+        l_apic[TPR] = tpr.value;
         
         /* Spurious-Interrupt Vector Register initialization. */
@@ -336 +343 @@
         svr.vector = VECTOR_APIC_SPUR;
         svr.lapic_enabled = true;
+        svr.focus_checking = true;
         l_apic[SVR] = svr.value;
-
-        l_apic[TPR] &= TPRClear;
 
         if (CPU->arch.family >= 6)

doc/arch/amd64

@@ -16 +16 @@
 
 SMP COMPATIBILITY
-        o Bochs 2.2.1
+        o Bochs 2.2.1 - 2.2.6
                 o 2x-8x AMD64 CPU
         o Simics 2.2.19

doc/arch/ia32

@@ -17 +17 @@
 
 SMP COMPATIBILITY
-        o Bochs 2.0.2 - Bochs 2.2.5
+        o Bochs 2.0.2 - Bochs 2.2.6
                 o 2x-8x 686 CPU
         o Simics 2.0.28 - Simics 2.2.19