Ignore:
Timestamp:
2006-09-05T21:06:59Z (19 years ago)
Author:
Jakub Jermar <jakub@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
d7e3f1ad
Parents:
5035eeb7
Message:

Handle more sparc64 traps and improve handling of already handled traps.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • kernel/arch/sparc64/include/trap/mmu.h

    r5035eeb7 re2bf639  
    6363.endm
    6464
    65 .macro FAST_DATA_ACCESS_MMU_MISS_HANDLER
     65.macro FAST_DATA_ACCESS_MMU_MISS_HANDLER tl
    6666        /*
    6767         * First, try to refill TLB from TSB.
     
    101101         */
    1021020:
    103         HANDLE_MMU_TRAPS_FROM_SPILL_OR_FILL
     103.if (\tl > 0)
     104        wrpr %g0, 1, %tl
     105.endif
    104106
    105107        wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate
     
    107109.endm
    108110
    109 .macro FAST_DATA_ACCESS_PROTECTION_HANDLER
     111.macro FAST_DATA_ACCESS_PROTECTION_HANDLER tl
    110112        /*
    111113         * First, try to refill TLB from TSB.
     
    116118         * The same special case as in FAST_DATA_ACCESS_MMU_MISS_HANDLER.
    117119         */
    118         HANDLE_MMU_TRAPS_FROM_SPILL_OR_FILL
     120.if (\tl > 0)
     121        wrpr %g0, 1, %tl
     122.endif
    119123
    120124        wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate
    121125        PREEMPTIBLE_HANDLER fast_data_access_protection
    122 .endm
    123 
    124 .macro MEM_ADDRESS_NOT_ALIGNED_HANDLER
    125         ba mem_address_not_aligned_handler
    126         nop
    127 .endm
    128 
    129 /*
    130  * Macro used to lower TL when a MMU trap is caused by
    131  * the userspace register window spill or fill handler.
    132  */
    133 .macro HANDLE_MMU_TRAPS_FROM_SPILL_OR_FILL
    134         rdpr %tl, %g1
    135         sub %g1, 1, %g2
    136         brz %g2, 0f                     ! if TL was 1, skip
    137         nop
    138         wrpr %g2, 0, %tl                ! TL--
    139         rdpr %tt, %g3
    140         cmp %g3, TT_SPILL_1_NORMAL
    141         be 0f                           ! trap from spill_1_normal?
    142         cmp %g3, TT_FILL_1_NORMAL
    143         bne,a 0f                        ! trap from fill_1_normal? (negated condition)
    144         wrpr %g1, 0, %tl                ! TL++
    145 0:
    146126.endm
    147127
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