Changeset e2ec980f in mainline for arch/ia64/src/cpu/cpu.c

Timestamp:

2005-11-09T01:21:46Z (19 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

b183865e

Parents:

0b5ac364

Message:

ia64 work.
Big cleanup of IA-64 interrupt processing.
Merge of interrupt.c and interrupt_handler.c.
Rewrite of ivt.S and interrupt.c.
Higher level interrupt handlers are now passed a vector number and a pointer to stack structure.

ia32 work.
ia32 has ordered writes. Until it deploys weaker memory ordering model, write_barrier() can be empty statement.

File:

• arch/ia64/src/cpu/cpu.c (modified) (2 diffs)

arch/ia64/src/cpu/cpu.c

@@ -4 +4 @@
 #include <arch/types.h>
 
-extern int IVT;
-
-
-
-
 void cpu_arch_init(void)
 {
-
-
-
-    int *p=&IVT;
-    volatile __u64 hlp,hlp2;
-
-
-    int psr = 0x2000;
+        int psr = 0x2000;
     
-
         __asm__  volatile (
-                "mov cr2 = %0;;\n"
-                "{mov psr.l = %1;;}\n"
+                "{mov psr.l = %0 ;;}\n"
                 "{srlz.i;"
-                "srlz.d;;}"
+                "srlz.d ;;}"
                 : 
-                : "r" (p), "r" (psr)
+                : "r" (psr)
         );
 
-
-
-        /*Switch register bank of regs r16 .. r31 to 1 It is automaticly cleared on exception*/
+        /* Switch to register bank 1. */
         __asm__ volatile 
         (
@@ -38 +22 @@
         );             
         
-
 }