Changeset f3a6c8e5 in mainline for arch/mips/src/exception.c
- Timestamp:
- 2005-09-10T01:16:19Z (19 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 9060bd1
- Parents:
- ffc277e
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
arch/mips/src/exception.c
rffc277e rf3a6c8e5 52 52 cp0_status_write(cp0_status_read() & ~ (cp0_status_exl_exception_bit | 53 53 cp0_status_um_bit)); 54 54 55 /* Save pstate so that the threads can access it */ 55 if (THREAD) 56 /* If THREAD->pstate is set, this is nested exception, 57 * do not rewrite it 58 */ 59 if (THREAD && !THREAD->pstate) 56 60 THREAD->pstate = pstate; 57 61 … … 64 68 case EXC_TLBS: 65 69 tlb_invalid(pstate); 70 break; 71 case EXC_CpU: 72 #ifdef FPU_LAZY 73 scheduler_fpu_lazy_request(); 74 #else 75 panic("unhandled Coprocessor Unusable Exception\n"); 76 #endif 66 77 break; 67 78 case EXC_Mod: … … 88 99 panic("unhandled Reserved Instruction Exception\n"); 89 100 break; 90 case EXC_CpU:91 #ifdef FPU_LAZY92 scheduler_fpu_lazy_request();93 #else94 panic("unhandled Coprocessor Unusable Exception\n");95 #endif96 break;97 101 case EXC_Ov: 98 102 panic("unhandled Arithmetic Overflow Exception\n"); … … 118 122 119 123 pstate->epc += epc_shift; 120 /* Probable not needed, but just for sure that nobody 121 * will continue accessing it */ 124 /* Set to NULL, so that we can still support nested 125 * exceptions 126 * TODO: We should probably set EXL bit before this command, 127 * nesting. On the other hand, if some exception occurs between 128 * here and ERET, it won't set anything on the pstate anyway. 129 */ 122 130 if (THREAD) 123 131 THREAD->pstate = NULL;
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