Changeset 1b03ed3 in mainline for kernel/arch/ia64/src/ivt.S

Timestamp:

2007-11-16T16:20:45Z (17 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

454889c

Parents:

9c2fb97

Message:

Support for six syscall arguments on ia64.

—iSupis line, and those below, will be ignored—

M kernel/arch/ia64/include/interrupt.h
M kernel/arch/ia64/src/ivt.S
M kernel/arch/ia64/src/interrupt.c
M uspace/lib/libc/arch/ia64/src/syscall.S

File:

• kernel/arch/ia64/src/ivt.S (modified) (5 diffs)

kernel/arch/ia64/src/ivt.S

@@ -34 +34 @@
 
 #define FRS_TO_SAVE 30
-#define STACK_ITEMS             (19 + FRS_TO_SAVE*2)
+#define STACK_ITEMS             (21 + FRS_TO_SAVE * 2)
 #define STACK_FRAME_SIZE        ALIGN_UP((STACK_ITEMS*STACK_ITEM_SIZE) + STACK_SCRATCH_AREA_SIZE, STACK_ALIGNMENT)
 
@@ -136 +136 @@
          */
         mov R_TMP = 0x2c00 ;;
-        cmp.eq p6,p5 = R_OFFS, R_TMP ;;
-        
-        /*
-         * From now on, if this is break_instruction handler, p6 is true and p5 is false.
-         * Otherwise p6 is false and p5 is true.
+        cmp.eq p6, p5 = R_OFFS, R_TMP ;;
+        
+        /*
+         * From now on, if this is break_instruction handler, p6 is true and p5
+         * is false. Otherwise p6 is false and p5 is true.
          * Note that p5 is a preserved predicate register and we make use of it.
          */
 
+(p6)    st8 [r31] = r38, -8 ;;          /* save in6 */
+(p6)    st8 [r31] = r37, -8 ;;          /* save in5 */
 (p6)    st8 [r31] = r36, -8 ;;          /* save in4 */  
 (p6)    st8 [r31] = r35, -8 ;;          /* save in3 */
@@ -149 +151 @@
 (p6)    st8 [r31] = r33, -8 ;;          /* save in1 */
 (p6)    st8 [r31] = r32, -8 ;;          /* save in0 */
-(p5)    add r31 = -40, r31 ;;
+(p5)    add r31 = -56, r31 ;;
     
         st8 [r31] = r30, -8 ;;          /* save old stack pointer */ 
@@ -179 +181 @@
         
         /*
-         * Inspect BSPSTORE to figure out whether it is necessary to switch to kernel BSPSTORE.
+         * Inspect BSPSTORE to figure out whether it is necessary to switch to
+         * kernel BSPSTORE.
          */
 (p1)    shr.u r30 = r28, VRN_SHIFT ;;
@@ -206 +209 @@
 
     /* 16. RSE switch to interrupted context */
-        cover                           /* allocate zerro size frame (step 1 (from Intel Docs)) */
-
-        add r31 = (STACK_SCRATCH_AREA_SIZE+(FRS_TO_SAVE*2*8)), r12 ;;
+        cover                           /* allocate zero size frame (step 1 (from Intel Docs)) */
+
+        add r31 = (STACK_SCRATCH_AREA_SIZE + (FRS_TO_SAVE * 2 * 8)), r12 ;;
 
         ld8 r30 = [r31], +8 ;;          /* load ar.bsp */