Changeset 3b712407 in mainline for arch/ia32/src/ia32.c


Ignore:
Timestamp:
2006-03-23T21:15:59Z (19 years ago)
Author:
Ondrej Palkovsky <ondrap@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
e1be3b6
Parents:
38ee55b
Message:

Fixed bad rflags masking in amd64.
Added TLS get address instruction emulation for mips.

File:
1 edited

Legend:

Unmodified
Added
Removed

  • arch/ia32/src/ia32.c

    r38ee55b r3b712407  
    112112/** Set Thread-local-storeage pointer
    113113 *
    114  * TLS pointer is set in FS register. Unfortunately the 64-bit
    115  * part can be set only in CPL0 mode.
    116  *
    117  * The specs says, that on %fs:0 there is stored contents of %fs register,
    118  * we need not to go to CPL0 to read it.
     114 * TLS pointer is set in GS register. That means, the GS contains
     115 * selector, and the descriptor->base is the correct address.
    119116 */
    120117__native sys_tls_set(__native addr)
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