Changeset 897ad60 in mainline

Timestamp:

2006-04-13T16:11:27Z (19 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

39cea6a

Parents:

963074b3

Message:

Replace assembly from pm.c with new inline functions defined in asm.h.

Location:

arch

Files:

• amd64/include/asm.h (modified) (2 diffs)
• amd64/src/pm.c (modified) (1 diff)
• ia32/include/asm.h (modified) (2 diffs)
• ia32/src/pm.c (modified) (3 diffs)

arch/amd64/include/asm.h

@@ -30 +30 @@
 #define __amd64_ASM_H__
 
+#include <arch/pm.h>
 #include <arch/types.h>
 #include <config.h>
@@ -198 +199 @@
 static inline void invlpg(__address addr)
 {
-        __asm__ volatile ("invlpg %0\n" :: "m" (*((__native *)addr)));
+        __asm__ volatile ("invlpg %0\n" :: "m" (*((__native *)addr)));
+}
+
+/** Load GDTR register from memory.
+ *
+ * @param gdtr_reg Address of memory from where to load GDTR.
+ */
+static inline void gdtr_load(struct ptr_16_64 *gdtr_reg)
+{
+        __asm__ volatile ("lgdt %0\n" : : "m" (*gdtr_reg));
+}
+
+/** Store GDTR register to memory.
+ *
+ * @param gdtr_reg Address of memory to where to load GDTR.
+ */
+static inline void gdtr_store(struct ptr_16_64 *gdtr_reg)
+{
+        __asm__ volatile ("sgdt %0\n" : : "m" (*gdtr_reg));
+}
+
+/** Load IDTR register from memory.
+ *
+ * @param idtr_reg Address of memory from where to load IDTR.
+ */
+static inline void idtr_load(struct ptr_16_64 *idtr_reg)
+{
+        __asm__ volatile ("lidt %0\n" : : "m" (*idtr_reg));
+}
+
+/** Load TR from descriptor table.
+ *
+ * @param sel Selector specifying descriptor of TSS segment.
+ */
+static inline void tr_load(__u16 sel)
+{
+        __asm__ volatile ("ltr %0" : : "r" (sel));
 }
 

arch/amd64/src/pm.c

@@ -216 +216 @@
         gdt_tss_setlimit(&gdt_p[TSS_DES], sizeof(struct tss) - 1);
 
-        __asm__("lgdt %0" : : "m"(gdtr));
-        __asm__("lidt %0" : : "m"(idtr));
+        gdtr_load(&gdtr);
+        idtr_load(&idtr);
         /*
          * As of this moment, the current CPU has its own GDT pointing
          * to its own TSS. We just need to load the TR register.
          */
-        __asm__("ltr %0" : : "r" ((__u16) gdtselector(TSS_DES)));
-}
+        tr_load(gdtselector(TSS_DES));
+}

arch/ia32/include/asm.h

@@ -31 +31 @@
 #define __ia32_ASM_H__
 
+#include <arch/pm.h>
 #include <arch/types.h>
 #include <config.h>
@@ -252 +253 @@
 }
 
+/** Load GDTR register from memory.
+ *
+ * @param gdtr_reg Address of memory from where to load GDTR.
+ */
+static inline void gdtr_load(struct ptr_16_32 *gdtr_reg)
+{
+        __asm__ volatile ("lgdt %0\n" : : "m" (*gdtr_reg));
+}
+
+/** Store GDTR register to memory.
+ *
+ * @param gdtr_reg Address of memory to where to load GDTR.
+ */
+static inline void gdtr_store(struct ptr_16_32 *gdtr_reg)
+{
+        __asm__ volatile ("sgdt %0\n" : : "m" (*gdtr_reg));
+}
+
+/** Load IDTR register from memory.
+ *
+ * @param idtr_reg Address of memory from where to load IDTR.
+ */
+static inline void idtr_load(struct ptr_16_32 *idtr_reg)
+{
+        __asm__ volatile ("lidt %0\n" : : "m" (*idtr_reg));
+}
+
+/** Load TR from descriptor table.
+ *
+ * @param sel Selector specifying descriptor of TSS segment.
+ */
+static inline void tr_load(__u16 sel)
+{
+        __asm__ volatile ("ltr %0" : : "r" (sel));
+}
+
 #endif

arch/ia32/src/pm.c

@@ -179 +179 @@
         idtr.limit = sizeof(idt);
         idtr.base = (__address) idt;
-        __asm__ volatile ("lgdt %0\n" : : "m" (gdtr));
-        __asm__ volatile ("lidt %0\n" : : "m" (idtr));  
+        gdtr_load(&gdtr);
+        idtr_load(&idtr);
         
         /*
@@ -214 +214 @@
          * to its own TSS. We just need to load the TR register.
          */
-        __asm__ volatile ("ltr %0" : : "r" ((__u16) selector(TSS_DES)));
+        tr_load(selector(TSS_DES));
         
         clean_IOPL_NT_flags();    /* Disable I/O on nonprivileged levels */
@@ -225 +225 @@
         struct descriptor *gdt_p = (struct descriptor *) cpugdtr.base;
 
-        __asm__ volatile ("sgdt %0\n" : : "m" (cpugdtr));
-
+        gdtr_store(&cpugdtr);
         gdt_setbase(&gdt_p[TLS_DES], tls);
         /* Reload gdt register to update GS in CPU */
-        __asm__ volatile ("lgdt %0\n" : : "m" (cpugdtr));
-}
+        gdtr_load(&cpugdtr);
+}