Changeset 897ad60 in mainline for arch/ia32/include/asm.h

Timestamp:

2006-04-13T16:11:27Z (19 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

39cea6a

Parents:

963074b3

Message:

Replace assembly from pm.c with new inline functions defined in asm.h.

File:

• arch/ia32/include/asm.h (modified) (2 diffs)

arch/ia32/include/asm.h

@@ -31 +31 @@
 #define __ia32_ASM_H__
 
+#include <arch/pm.h>
 #include <arch/types.h>
 #include <config.h>
@@ -252 +253 @@
 }
 
+/** Load GDTR register from memory.
+ *
+ * @param gdtr_reg Address of memory from where to load GDTR.
+ */
+static inline void gdtr_load(struct ptr_16_32 *gdtr_reg)
+{
+        __asm__ volatile ("lgdt %0\n" : : "m" (*gdtr_reg));
+}
+
+/** Store GDTR register to memory.
+ *
+ * @param gdtr_reg Address of memory to where to load GDTR.
+ */
+static inline void gdtr_store(struct ptr_16_32 *gdtr_reg)
+{
+        __asm__ volatile ("sgdt %0\n" : : "m" (*gdtr_reg));
+}
+
+/** Load IDTR register from memory.
+ *
+ * @param idtr_reg Address of memory from where to load IDTR.
+ */
+static inline void idtr_load(struct ptr_16_32 *idtr_reg)
+{
+        __asm__ volatile ("lidt %0\n" : : "m" (*idtr_reg));
+}
+
+/** Load TR from descriptor table.
+ *
+ * @param sel Selector specifying descriptor of TSS segment.
+ */
+static inline void tr_load(__u16 sel)
+{
+        __asm__ volatile ("ltr %0" : : "r" (sel));
+}
+
 #endif